DLA MIL-PRF-19500 558 J-2013 SEMICONDUCTOR DEVICE UNITIZED PNP SILICON SWITCHING FOUR TRANSISTOR ARRAY TYPES 2N6987 2N6987U AND 2N6988 JAN JANTX JANTXV JANS JANSM JANSD JANSP JANSL.pdf

1、 MIL-PRF-19500/558J 29 March 2013 SUPERSEDING MIL-PRF-19500/558H 23 May 2011 PERFORMANCE SPECIFICATION SHEET SEMICONDUCTOR DEVICE, UNITIZED, PNP, SILICON, SWITCHING, FOUR TRANSISTOR ARRAY, TYPES 2N6987, 2N6987U, AND 2N6988, JAN, JANTX, JANTXV, JANS, JANSM, JANSD, JANSP, JANSL, JANSR, JANSF, JANSG, A

2、ND JANSH This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product described herein shall consist of this specification sheet and MIL-PRF-19500. 1. SCOPE 1.1 Scope. This specification covers the performance require

3、ments for PNP, silicon, switching transistors, four independent chip array. Four levels of product assurance are provided for each device type as specified in MIL-PRF-19500. Radiation hardness assurance (RHA) level designators “M”, “D”, “P“, “L”, “R”, “F”, “G”, and “H” are appended to the device pre

4、fix to identify devices which have passed RHA requirements. 1.2 Physical dimensions. See figures 1, 2, 3, and 4 (14-pin dual-in-line, 14-pin flat-pack, and 20-pin leadless chip carrier). 1.3 Maximum ratings, unless otherwise specified TA= +25C. (1) PTTA= +25C (2) PTTA(AM)= +25C (2) RJA(3) RJA(AM)(3)

5、 (4) VCBO(5) VEBO(5) VCEO(5) IC(3) TJand TSTGW W C/W C/W V dc V dc V dc mA dc C 2N6987 1.5 N/A 85 N/A 60 5 60 600 -65 2N6987U 1.0 N/A 160 N/A 60 5 60 600 to 2N6988 1.0 1.0 175 23 60 5 60 600 +200 (1) Maximum voltage between transistors shall be 500 V dc. (2) For derating see figures 5, 6, 7, and 8.

6、(3) For thermal impedance graphs, see figures 9, 10, 11, and 12. (4) Thermally conductive adhesive mount to infinite heat sink. (5) Ratings apply to each transistor in the array. AMSC N/A FSC 5961 INCH-POUND * Comments, suggestions, or questions on this document should be addressed to DLA Land and M

7、aritime, ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductordla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at https:/assist.dla.mil. The documentation and process conversion me

8、asures necessary to comply with this document shall be completed by 28 June 2013. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 2 FIGURE 1. Dimensions and configuration for type 2N6987. Provided by IHSNot for ResaleNo reproductio

9、n or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 3 Symbol Inches Millimeters Notes Min Max Min Max BH .200 5.08 LW .014 .023 0.36 0.58 8 LW1.030 .070 0.76 1.78 4, 8 LT .008 .015 0.20 0.38 8 BL .785 19.94 4 BW .220 .310 5.59 7.87 4 BW1.290 .320 7.37 8.13 7 LS .100 BSC 2.54 BS

10、C 5, 9 LL .125 .200 3.18 5.08 LL1.150 3.81 LO2.015 .060 0.38 1.52 3 LO1.098 2.49 6 LO .005 0.13 6 0 15 0 15 NOTES: 1. Dimensions are in inches. 2. Millimeters are given for information only. 3. Index area; a notch or pin one identification mark shall be located adjacent to pin one and shall be locat

11、ed within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. 4. The minimum limit for dimension LW1may be .023 inch (0.58 mm) for lead numbers 1, 7, 8, and 14 only. 5. Dimension LO2shall be measured from the seating plane to the base plane. 6.

12、 This dimension allows for off-center lid, meniscus, and glass overrun. 7. The basic pin spacing is .100 inch (2.54 mm) between centerlines. Each pin centerline shall be located within .010 inch (0.25 mm) of its exact longitudinal position relative to pins 1 and 14. 8. Applies to all four corners (l

13、ead numbers 1, 7, 8, and 14). 9. Lead center when is 0 degrees. BW1shall be measured at the centerline of the leads. 10. All leads: Increase maximum limit by .003 inch (0.08 mm) measured at the center of the flat, when lead finish A is applied. Pointed or round lead ends are allowed. 11. Twelve spac

14、es. 12. No organic or polymeric materials shall be molded to the bottom of the package to cover leads. 13. For terminal connections, see figure 4. 14. In accordance with ASME Y14.5M, diameters are equivalent to x symbology. FIGURE 1. Dimensions and configuration for type 2N6987 - Continued. Provided

15、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 4 FIGURE 2. Physical dimensions for type 2N6988. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 5 Dimensions Dimensions S

16、ymbol Inches Millimeters Notes Symbol Inches Millimeters Notes Min Max Min Max Min Max Min Max CH .030 .115 0.76 2.92 BW3.030 0.76 LW .010 .019 0.25 0.48 7 LS .050 BSC 1.27 BSC 6, 8 TL .008 .015 0.20 0.38 12 LT .003 .006 0.076 0.152 7 BL .280 7.11 5 LL .250 .370 6.35 9.40 BW .240 .260 6.10 6.60 LD2.

17、005 .040 0.13 1.02 4 LU .290 7.37 5 LO .005 0.13 9, 10 BW2.125 3.18 LO3.004 0.10 13 30 90 30 90 14 NOTES: 1. Dimensions are in inches. 2. Millimeters are given for general information only. 3. Index area: A notch or pin one identification mark shall be located adjacent to pin one and shall be locate

18、d within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. Alternatively, a tab (dim TL) may be used to identify pin one. 4. Dimension LD2shall be measured at the point of exit of the lead from the body. 5. This dimension allows for off-cente

19、r lid, meniscus, and glass overrun. 6. The basic pin spacing is .050 inch (1.27 mm) between centerlines. Each pin centerline shall be located within .005 inch (0.13 mm) of its exact longitudinal position relative to pins 1 and 14. 7. All leads: Increase maximum limit by .003 inch (0.08 mm) measured

20、at the center of the flat when the lead finish is solder. 8. Twelve spaces. 9. Applies to all four corners (leads number 2, 6, 9, and 13). 10. Dimension LO may be .000 inch (0.00 mm if leads number 2, 6, 9, and 13) bend toward the cavity of the package within one lead width from the point of entry o

21、f the lead into the body or if the leads are brazed to the metallized ceramic body. 11. No organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 12. Optional, see note 1. If a pin one identification mark is used in addition to this tab, the minimum limit of

22、dimension TL does not apply. 13. Applies to leads number 1, 7, 8, and 14. 14. Lead configuration is optional within dimension BW except dimensions LW and LT apply. 15. In accordance with ASME Y14.5M, diameters are equivalent to x symbology. 16. Pins 1, 7, 8, and 14 are collectors. 17. Pins 2, 6, 9,

23、and 13 are bases. 18. Pins 3, 5, 10, and 12 are emitters. 19. Pins 4 and 11 are no contacts. FIGURE 2. Physical dimensions for type 2N6988 - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 6 Symbol Dimensions Inches Mill

24、imeters Min Max Min Max A .073 .085 1.85 2.16 A1.063 .075 1.60 1.90 D .345 .355 8.76 9.02 D1.195 .205 4.95 5.21 D2.050 TYP 1.27 TYP D3.070 .080 1.76 2.03 E .025 REF 0.64 REF L1.050 REF 1.27 REF L2.080 .090 2.03 2.28 NOTES: 1. Dimensions are in inches. 2. Millimeters equivalents are given for general

25、 information only. 3. Unless otherwise specified, tolerance is .005 inch (0.13 mm). 4. For terminal connections, see figure 4. 5. In accordance with ASME Y14.5M, diameters are equivalent to x symbology. FIGURE 3. Physical dimensions for type 2N6987U. 1 20 18 14 13 4 8 1 PIN 1 INDEX 9 Provided by IHS

26、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 7 14-lead flat-package or dual-in-line (top view) 20 pin leadless chip carrier (top view). FIGURE 4. Schematic and terminal connections. Provided by IHSNot for ResaleNo reproduction or networking pe

27、rmitted without license from IHS-,-,-MIL-PRF-19500/558J 8 1.4 Primary electrical characteristics. Characteristics apply to each transistor in the array. Limits hFE2(1) hFE4(1) CoboSwitching VCE= 10 V dc IC= 1.0 mA dc VCE= 10 V dc IC= 150 mA dc VCB= 10 V dc IE= 0 100 kHz f 1 MHz ton see figure 13 tof

28、f see figure 14 pF ns ns Min Max 100 450 100 300 8 45 300 Limits hfe VCE(sat)2(1) VBE(sat)2(1) VCE= 20 V dc IC= 50 mA dc f = 100 MHz IC= 500 mA dc IB= 50 mA dc IC= 500 mA dc IB= 50 mA dc Min Max 2.0 8.0 V dc 1.6 V dc 2.6 (1) Pulsed (see 4.5.1). 2. APPLICABLE DOCUMENTS 2.1 General. The documents list

29、ed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, doc

30、ument users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks f

31、orm a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-19500 - Semiconductor Devices, General Specification for. DEPARTMENT OF DEFENSE STANDARD

32、S MIL-STD-750 - Test Methods for Semiconductor Devices. * (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or https:/assist.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of prece

33、dence. Unless otherwise noted herein or in the contract, in the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption

34、 has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 9 3. REQUIREMENTS 3.1. General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein. 3.2. Qualification. Devices furnish

35、ed under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list (QML) before contract award (see 4.2 and 6.3). 3.3. Abbreviations, symbols, and definitions. Abbreviations, symbols,

36、and definitions used herein shall be as specified in MIL-PRF-19500. PCB Printed circuit board. RJAThermal resistance junction to ambient. RJA(AM)Thermal resistance ambient (adhesive mount to PCB). TA(AM)Temperature ambient (adhesive mount to PCB). 3.4 Interface requirements and physical dimensions.

37、The interface requirements and physical dimensions shall be as specified in MIL-PRF-19500 and on figures 1, 2, 3, and 4 herein. 3.4.1 Lead finish. Lead finish shall be solderable in accordance with MIL-STD-750, MIL-PRF-19500, and herein. Where a choice of lead finish is desired, it shall be specifie

38、d in the acquisition document (see 6.2). 3.4.2 Schematic and terminal connections. The schematic and terminal connections shall be as shown on figure 4. 3.5 Radiation hardness assurance (RHA). Radiation hardness assurance requirements, PIN designators, and test levels shall be as defined in MIL-PRF-

39、19500. 3.6 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.7 Electrical test requirements. The electrical test requirements shall be as specified in table I. 3.8 Marking. Marking

40、 shall be in accordance with MIL-PRF-19500. The radiation hardened designator M, D, P, L, R, F, G, or H shall immediately precede (or replace) the device “2N” identifier (depending upon degree of abbreviation required). 3.9. Workmanship. Semiconductor devices shall be processed in such a manner as t

41、o be uniform in quality and shall be free from other defects that will affect life, serviceability, or appearance. 4. VERIFICATION 4.1 Classification of inspections. The inspection requirements specified herein are classified as follows: a. Qualification inspection (see 4.2). b. Screening (see 4.3).

42、 c. Conformance inspection (see 4.4 and table I and II). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-PRF-19500/558J 10 4.2 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-19500 and as specified herein. 4

43、.2.1 Group E qualification. Group E inspection shall be performed for qualification or re-qualification only. In case qualification was awarded to a prior revision of the specification sheet that did not request the performance of table III tests, the tests specified in table III herein that were no

44、t performed in the prior revision shall be performed on the first inspection lot of this revision to maintain qualification. * 4.3 Screening (JANS, JANTX and JANTXV levels only). Screening shall be in accordance with table E-IV of MIL-PRF-19500 appendix E, and as specified herein. The following meas

45、urements shall be made in accordance with table I herein. Devices that exceed the limits of table I herein shall not be acceptable. Screen (see appendix E, table E-IV of MIL-PRF-19500) Measurements JANS level JANTX and JANTXV levels (1) 3c Thermal impedance, method 3131 of MIL-STD-750, see 4.3.2. Th

46、ermal impedance, method 3131 of MIL-STD-750, see 4.3.2. 9 ICBO2and hFE4Not applicable. 10 24 hours minimum. 24 hours minimum. 11 ICBO2and hFE4 ICBO2= 100 percent of initial value or 5 nA dc, whichever is greater; hFE4= 15 percent of initial value. ICBO2and hFE412 See 4.3.1. See 4.3.1. 13 Subgroups 2

47、 and 3 of table I herein; ICBO2= 100 percent of initial value or 5 nA dc, whichever is greater; hFE4= 15 percent of initial value. Subgroup 2 of table I herein; ICBO2= 100 percent of initial value or 5 nA dc, whichever is greater; hFE4= 15 percent of initial value. (1) Shall be performed anytime aft

48、er temperature cycling, screen 3a; TX and TXV do not need to be repeated in screening requirements. 4.3.1 Power burn-in conditions. Power burn-in conditions are as follows: VCB= 10 - 30 V dc; PT= 1.5 W for 2N6987; PT= 1.0 W for 2N6987U, and PT= 1.0 W for 2N6988. TAambient rated as defined in 1.3. NOTE: No heat sink or forced air-cooling on the devices shall be permitted. Power ratings apply to total package. With approval of the qualifying activity and preparing activity, alternate burn-in criteria (hours, bias conditions, TJ, and mounting conditions) may be used for JANTX and