DLA SMD-5962-01504 REV D-2011 MICROCIRCUIT HYBRID CUSTOM FIELD EFFECT TRANSISTOR 500 VOLT WITH GATE PROTECTION.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added vendor cages U4388, 51651 and 57363. Added Resistance junction-to-case (RJC) to paragraph 1.3. Added paragraphs 3.2.7, 4.3.3.1, and 5.1.2. Changed paragraphs 1.2, 1.2.2, 1.2.3, 1.3, 1.4, 2.1, 3.1, 4.1, 4.1.1, 4.2, 4.3.3, and 4.3.6. Table I;

2、 made changes to the the tests VGS(th)1, VGS(th)2, VGS(th)3, RDS(ON)1, RDS(ON)2, IDSS1, td(ON), tr, td(off), and tf. Made changes to Figure 1. -sld 05-12-07 Raymond Monnin B Table I; Changed the max limit for the Static drain to source “on“ state resistance tests RDS(ON)1from .22 max to .25 max and

3、RDS(ON)2 from .45 max to .465 max. -sld 07-09-17 Robert M. Heber C Table I: Turn off delay time, change the max limit of 235 ns to 265 ns and Fall time, change the max limit of 90 ns to 95 ns. -gz 11-07-11 Charles F. Saffle D Correct paragraph 1.3, Resistance, junction to case, change 0.7C/W to 1.2C

4、/W. -gz 11-08-01 Charles F. Saffle REV SHEET REV D D SHEET 15 16 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Greg Cecil COLUMBUS, OHIO 43218-3990 http:/

5、www.landandmaritime.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Raymond Monnin MICROCIRCUIT, HYBRID, CUSTOM, FIELD EFFECT TRANSISTOR, 500 VOLT, WITH GATE PROTECTION DRAWING APPROVAL DATE 01-03-05 AMSC N/A REVISION LEVEL D SIZE A

6、 CAGE CODE 67268 5962-01504 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E449-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01504 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC

7、 FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiatio

8、n hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 01504 01 H X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1

9、.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circu

10、it function as follows: Device type Vendor similar PIN Circuit function 01 12787, NHI-1671, MSK1667H Field Effect Transistor, 500 V, N-channel with gate protection circuitry 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level.

11、All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. Thi

12、s level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening an

13、d In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) wi

14、th exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality

15、 class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01504 DLA LAND AND MARITI

16、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 4 or 10 1/ Hybrid package 1.2.5 Lead finish. The lead

17、finish shall be as specified in MIL-PRF-38534 and figure 1 herein. 1.3 Absolute maximum ratings. 2/ Power dissipation (PD) 3/ 25 W Breakdown voltage, drain to source (V(BR)VSS) 500 V dc minimum Gate to source voltage range (VGS) 14.2 V dc Source drain diode voltage (VDS) 500 V dc Drain current maxim

18、um 4/ 12 A dc Pulsed drain current maximum 5/ 30 A dc Junction temperature (TJ) +150C Isolation voltage (VISO) 70000 ft altitude . 500 V dc Resistance, junction to case (RJC) 6/ 1.2C/W Lead temperature (TL): 0.063 inches (1.60 mm) from case for 10 seconds +300C Case operating temperature range (TC)

19、-55C to +125C Storage temperature range -55C to +150C 1.4 Recommended operating conditions. Gate to source voltage, threshold range (VGS(th)1) +2.0 V dc to +4.0 V dc Source current (IS) 8.0 A dc steady state, 20 A peak pulsed Drain current (ID1) TC= +25C 8.0 A dc steady state, 20 A peak pulsed 1/ Fo

20、r the 10 lead package, configuration B in figure 1, pins 1 through 4 are tied together for the DRAIN (pin 1) and pins 5 through 8 are tied together for the SOURCE (pin 2). 2/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum level

21、s may degrade performance and affect reliability. 3/ Derate linearly 0.16W/C for TC +25C. PD= TJ- TC/ RJC. 4/ Repetitive rating, pulse width limited by maximum junction temperature. 5/ Pulsed. Conditions for pulse measurement shall be as specified in section 4 of MIL-STD-750. 6/ When tested per meth

22、od 3161of MIL-STD-750, with the following conditions: IM= 10 mA, IH=3 A, tH= 15 seconds, VH= 8.4 V, tMD= 100 s, and tSW= 10 s. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01504 DLA LAND AND MARITIME COLUM

23、BUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues

24、 of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-750 - Test Method Standard for Semiconductor Devices. MIL-STD-883 - Test Method Standard M

25、icrocircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/

26、quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents

27、 are those cited in the solicitation. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JESD22-A101 - Steady State Temperature Humidity Bias Life Test. JESD22-A110 - Test Method A110 Highly Accelerated Temperature and Humidity Stress Test (HAST). JESD22-A113 - Test Method A113 Preconditioning of Plastic Surface

28、 Mount Devices Prior to Reliability Testing. JESD22-B101 - Test Method B101 External Visual. J-STD-033 - Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices. (Copies of these documents are available online at http:/www.jedec.org/ or from the Electronic

29、s Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and

30、regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests here

31、in or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the ap

32、plicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. Class D parts are defined by the requirements as specified in 4.3.6 and herein. Class D, non-hermetic parts supplied to this drawing shall me

33、et the requirements of this drawing however, tests which are relevant to non-hermetic technologies should be used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01504 DLA LAND AND MARITIME COLUMBUS, OHIO 43

34、218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figu

35、re 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Schematic diagram. The schematic diagram shall be as specified on figure 3. 3.2.4 Switching waveform. The switching waveform shall be as specified on figure 4. 3.2.5 Rework. The rework requirements sh

36、all be in accordance with MIL-PRF-38534 except that the limits on polymer element replacement shall not apply as long as the substrate material is not damaged and all the bond pads are inspected in accordance with documented inspection requirements prior to the installment of the replacement compone

37、nts. 3.2.6 Unique circuit elements. The circuit elements in the following table are unique to this application and are not adequately verifiable by testing the completed part, and shall not be substituted: Device type Reference Designator as specified on Figure 3 Part Number (Source) 01 Q1 APT5020DN

38、 (0DY74) 3.2.7 High voltage spacing details. These parts are intended for high altitude, high voltage applications in extreme environmental conditions. Internal conductors over 200 V shall have a .007 inch minimum spacing between any other conductive surface. Layout dimensions shall be available for

39、 user verification of dimensions. If the internal cavity contains helium, the helium shall be 15 percent by volume maximum. Critical spacing for external dimensions shall be as defined in figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performa

40、nce characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Mar

41、king of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the m

42、anufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which

43、, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime-VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer

44、in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime-VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required

45、 in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01504 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEV

46、EL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol 1/ Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Breakdown voltage, drain to source V(BR)DSSMethod 3407, Bias condition C, VGS= 0 V dc, ID= 250 dc

47、 1 01 500 V dc Gate to source voltage (threshold) VGS(th)1Method 3403, VDS= VGS, ID= 1.0 mA dc 1 01 2.0 4.0 V dc VGS(th)22 1.0 VGS(th)33 5.0 Gate Current IGSS1Method 3411, VGis applied with respect to VGATE_RTN, VDS= 0, VGS= +10 V dc 1,2,3 01 0.9 1.1 mA IGSS2Method 3411, VGis applied with respect to

48、 VGATE_RTN, VDS= 0, VGS= -10 V dc -1.1 -0.9 Gate Protection VGZMethod 3411, VGis applied with respect to VGATE_RTN, VDS= 0, IG= 10 mA dc 1,2,3 01 13.8 18.5 V Method 3411, VGis applied with respect to VGATE_RTN, VDS= 0, IG= -10 mA dc -18.5 -13.8 Static drain to source “on“ state resistance RDS(ON)1Method 3421, Condition A, Pulsed, VGS= 10 V dc, ID= 8 A dc 1 01 0.25 RDS(ON)22 0.465 Forward voltage (source drain diode) VSDMethod 4011, VGS= 0 V dc, IF= 1.0 A dc 1 01 1.3 V dc Drain Current (leakage) IDSS1M