DLA SMD-5962-01527 REV A-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS OCTAL D-TYPE FLIP-FLOP WITH MASTER RESET TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update dimensions of case outline X to figure 1. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 12-12-19 Thomas M. Hess REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS S

2、HEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED B

3、Y Thanh V. Nguyen APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, ADVANCED CMOS, OCTAL D-TYPE FLIP-FLOP WITH MASTER RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 05-05-25 REVISION LEVEL A SIZE A CAGE CODE 67268 5962-01527 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E065-13 Pr

4、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assura

5、nce class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is refle

6、cted in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F 01527 01 V X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator

7、. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit fun

8、ction 01 54ACT273 Octal D-type flip-flop with master reset, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to

9、 MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 20 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provid

10、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC)

11、 -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC + 0.5 V dc 4/ DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc 4/ DC input/output clamp current (IIK, IOK) 20 mA DC output current (per pin) (IOUT) . 50 mA DC VCCor GND current (per output pin) (ICC, IGND) 100 mA Maximu

12、m power dissipation (PD) . 500 mW Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) +4.5 V

13、 dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage range (VOUT). +0.0 V dc to VCCMinimum high level input voltage (VIH) . +2.0 V dc Maximum low level input voltage (VIL) +0.8 V dc Maximum high level output current (IOH) -24 mA Maximum low level output current (IOL) +24 mA Maxi

14、mum input rise or fall time rate (t/V) . 8 ns/V Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features. Device type 01: Maximum total dose available (dose rate = 50 300 rads (Si)/s) 300 krads (Si) 5/ No Single Event Latchup (SEL) occurs at LET (see 4.4.4.2) . 93 MeV-cm2/mg 5/ 1

15、/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply

16、 over the full specified VCCrange and case temperature range of -55C to +125C. Unused inputs must be held high or low. 4/ The input negative voltage rating may be exceeded provided that the input clamp current rating is observed. 5/ Limits obtained during technology characterization/qualification, g

17、uaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME C

18、OLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the is

19、sues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stand

20、ard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Ord

21、er Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID

22、 STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD20 - Standard for Description of 54/74ACXXXXX and 54/74ACTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arli

23、ngton, VA 22201). ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document is available online at http:/www.astm.org/ or from ASTM International, 100 Barr Harbor Drive

24、, P. O. Box C700, West Conshohocken, PA 19428-2959). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents may also be available in or through libraries or other informational services.) 2.3 Order of p

25、recedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item req

26、uirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described here

27、in. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU

28、IT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure

29、 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on figure 5. 3.2.6 Switching waveform

30、s and test circuit. The switching waveforms and test circuit shall be as specified on figure 6. 3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring ac

31、tivity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperatu

32、re range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may

33、also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V

34、shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-

35、38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device cla

36、sses Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or

37、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Symbol Test conditio

38、ns 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type and device class VCCGroup A subgroups Limits 4/ Unit Min Max Positive input clamp voltage 3022 VIC+ For input under test, IIN= 1.0 mA All Q, V 0.0 V 1 0.4 1.5 V Negative input clamp voltage 3022 VIC- For input under test

39、, IIN= -1.0 mA All Q, V Open 1 -0.4 -1.5 V High level output voltage 3006 VOH5/ For all inputs affecting output under test, VIN= 2.0 V or 0.8 V For all other inputs, VIN= VCCor GND IOH= -50 A All All 4.5 V 1, 2, 3 4.4 V 5.5 V 5.4 IOH= -24 mA All All 4.5 V 1 3.86 2, 3 3.70 5.5 V 1 4.86 2, 3 4.70 IOH=

40、 -50 mA All All 5.5 V 1, 2, 3 3.85 Low level output voltage 3007 VOL5/ For all inputs affecting output under test, VIN= 2.0 V or 0.8 V For all other inputs, VIN= VCCor GND IOL= 50 A All All 4.5 V 1, 2, 3 0.1 V 5.5 V 0.1 IOL= 24 mA All All 4.5 V 1 0.36 2, 3 0.50 5.5 V 1 0.36 2, 3 0.50 IOL= 50 mA All

41、All 5.5 V 1, 2, 3 1.65 Input leakage current high 3010 IIH For input under test, VIN= VCCFor all other inputs, VIN= VCCor GND All All 5.5 V 1 0.1 A 2, 3 1.0 Input leakage current low 3009 IIL For input under test, VIN= GND For all other inputs, VIN= VCCor GND All All 5.5 V 1 -0.1 A 2, 3 -1.0 Quiesce

42、nt supply current, output high 3005 ICCHVIN= VCCor GND IOUT= 0.0 A All All 5.5 V 1 4.0 A 2, 3 80.0 M, D, P, L, R, F 6/ 01 Q, V 5.5 V 1 50.0 Quiescent supply current, output low 3005 ICCLVIN= VCCor GND IOUT= 0.0 A All All 5.5 V 1 4.0 A 2, 3 80.0 M, D, P, L, R, F 6/ 01 Q, V 5.5 V 1 50.0 See footnotes

43、at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-01527 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance character

44、istics - Continued. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type and device class VCCGroup A subgroups Limits 4/ Unit Min Max Quiescent supply current delta, TTL input levels 3005 ICC7/ For input under test, V

45、IN= VCC- 2.1 V For all other inputs, VIN= VCCor GND All All 5.5 V 1, 2, 3 1.6 mA Input capacitance 3012 CIN TC = 25C See 4.4.1c All All GND 4 10 pF Power dissipation capacitance CPD8/ TC= 25C See 4.4.1c All All 5.0 V 4 55 pF Low level ground bounce noise VGBL9/ VLD= 2.5 V IOL= 24 mA See figure 5 All

46、 Q, V 4.5 V 4 2000 mV High level ground bounce noise VGBH9/ VLD= 2.5 V IOH= -24 mA See figure 5 All Q, V 4.5 V 4 2000 mV Functional tests 3014 10/ VIN= 2.0 V or 0.8 V Verify output VOUTSee 4.4.1b All All 4.5 V 7, 8 L H 5.5 V 7, 8 L H Propagation delay time, CP to Qn 3003 tPHL1, tPLH1 11/ CL= 50 pF m

47、inimum RL= 500 See figure 6 All All 4.5 V 9 1.0 9.0 ns 10, 11 1.0 10.0 Propagation delay time, MR to Qn 3003 tPHL2 11/ All All 4.5 V 9 1.0 9.5 ns 10, 11 1.0 11.0 Maximum clock frequency fMAX12/ All All 4.5 V 9 95 MHz 10, 11 85 Setup time, high or low, Dn to CP ts12/All All 4.5 V 9, 10, 11 5.0 ns Hol

48、d time, high or low, Dn to CP th12/All All 4.5 V 9, 10, 11 2.0 ns CP pulse width, high or low tw112/All All 4.5 V 9, 10, 11 5.0 ns MR pulse width, low tw212/All All 4.5 V 9, 10, 11 5.0 ns Recovery time, MR to CP trec12/All All 4.5 V 9, 10, 11 4.0 ns 1/ For tests not listed in the referenced MIL-STD-883, e.g. VGBL, VGBH, utilize the general test procedure under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I herein. Output terminals not designated shall be hi