DLA SMD-5962-02517 REV B-2011 MICROCIRCUITS MEMORY DIGITAL CMOS 128M X 8 bit STACKED DIE(1Gbit) SYNCHRONOUS DRAM (SDRAM) MODULE.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A tREFin table I corrected to 128 ms max vs min value. Editorial and boilerplate changes. ksr 04-04-06 Raymond Monnin B Update boilerplate for 5 year review. lhl 11-06-17 Charles F. Saffle REV B B B B B SHEET 35 36 37 38 39 REV B B B B B B B B B B

2、B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIR

3、CUIT DRAWING CHECKED BY Rajesh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 128M X 8 bit STACKED DIE(1Gbit) SYNCHRONOUS DRAM (SDRAM), MODULE AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 02 12 17 AMSC

4、 N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-02517 SHEET 1 OF 39 DSCC FORM 2233 APR 97 5962-E392-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02517 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 R

5、EVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case out

6、lines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application envir

7、onment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 02517 01 N X B Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device

8、classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a

9、non-RHA device. 1.2.2 Device type(s). The device type(s) identify 128M x 8 bit SDRAM circuits utilizing vertical stacking technology as follows: Device Type Generic Number Circuit Function No. Die in Stack 01 SD128Mx84 16M x 8 bit x 8 bank, synchronous DRAM (1 Gbit) 4 Dice 02 SD128Mx88 8M x 8 bit x

10、16 bank, synchronous DRAM (1 Gbit) 8 Dice 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device Class Device Requirements Documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JA

11、N class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1/ N Certification and qualification to MIL-PRF-38535 for plastic encapsulated microcircuit (PEM). 2/ Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MI

12、L-STD-1835 and as follows: Outline Letter Descriptive Designator Terminals Package Style X See figure 1 54 Plastic small outline package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, Q and V or MIL-PRF-38535, appendix A for device class M. 1/ For this draw

13、ing, device class M shall not apply. 2/ A device outside the traditional performance environment; a plastic encapsulated microcircuit (PEM). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02517 DLA LAND AND

14、MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ 4/ Supply voltage range, (VCC) - -0.5 V dc to +4.6 V dc Voltage range on any input pin - -0.5 V dc to +4.6 V dc Voltage range on any output pin - -0.5 V dc to Vcc +0.5V dc Short-circuit

15、 output current - 50 mA Power dissipation (-01 & -02) - 2 W Operating free-air temperature range, (TA) - -40C to +85C Storage temperature range, - -55C to +125C Thermal resistance, junction-to-case, (JC): Case X (-01) - 7.7C/W (-02) - 15C/W 1.4 Recommended operating conditions. Supply voltage range,

16、 (VCC) - +3.0 V dc to +3.6 V dc Supply voltage, (VSS) - 0 V dc High-level input voltage, (VIH) - +2.0 V dc to Vcc +0.3 V dc Low-level input voltage, (VIL) - -0.3 V dc to +0.8 V dc Operating free-air temperature range, (TA) - -40C to +85C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standard

17、s, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrate

18、d Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDB

19、K-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict betwe

20、en the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3/ Stresses above the absolute maximum rating may cause permanent damag

21、e to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ All voltage values in this drawing are with respect to VSS Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

22、 A 5962-02517 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the

23、device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as speci

24、fied herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q and V. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 T

25、erminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Block diagram(s). The block diagram(s) shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specif

26、ied on figure 5. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperatu

27、re range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.4.1 Functional Tests. Listed below is a set of required test patterns to be used in conjunction with table I fo

28、r the functional tests of Subgroups 7 and 8 as well as the A.C. parametric tests in Subgroups 9, 10 and 11. These tests have been determined to effectively stress sensitivities related to address and data pattern as well as functionally test the device to be supplied to this specification. A.C. para

29、metric limits are tested by using the limit values as input conditions and measurement delays of the timing sets associated with Subgroups 7 and 8. Additional test patterns may also be used. a. Walking 0101 Pattern Full Page Burst / Sequential (Vmin) b. Walking FEFE Pattern Full Page Burst / Sequent

30、ial Vmax) c. March 00/FF Pattern 8 Byte Burst / Interleave (Vmin) d. March FF/00 Pattern 8 Byte Burst / Interleave (Vmax) e. March AA/55 Pattern 8 Byte Burst / Interleave (Vmin) f. March 55/AA Pattern 8 Byte Burst / Interleave (Vmax) g. March FF/00 Pattern 1 Byte Burst / Sequential (Vmin) h. March 0

31、0/FF Pattern 1 Byte Burst / Sequential (Vmax) i. March 66/33 Pattern 1 Byte Burst / Sequential (Vmin) j. March 33/66 Pattern 1 Byte Burst / Sequential (Vmax) k. Refresh Pause Checkerboard (Vmin) l. Refresh Pause Checkerboard (Vmax) m. Refresh Pause Checkerboard Bar (Vmin) n. Refresh Pause Checkerboa

32、rd Bar (Vmax) 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ o

33、n the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q and V shall be a “QML“ or “Q“ as required i

34、n MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02517 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. For device

35、classes N, Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for t

36、his drawing shall affirm that the manufacturers product meets, for device classes N, Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 shall be provided with each lot of micr

37、ocircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. For device Classes N, Q, and V, sampling and inspection procedure shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall

38、 not affect the form, fit, or function as described herein. 4.2 Screening. For device Classes N, Q, and V screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device clas

39、ses N, Q, and V. a. Temperature and voltage accelerated burn-in shall be employed for the SDRAM. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circu

40、it shall be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and pow

41、er dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (1) TA= +135C, VCC= 4.0V (2) Test duration: 72 hours for classes N & Q, and 100 hours for class V. b. Interim and final electrical test parameters shall be as specified in table IIA herein. (1) Temp

42、erature and voltage accelerated dynamic burn-in (Method 1015 of MIL-STD-883, Test Condition D). c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.2.2 Additional criteria for device class N. a. Temperature cyclin

43、g per Method 1010, condition B, 10 cycles. b. Post burn-in PDA is 5% maximum for subgroups 1 and 7 failures. 4.3 Qualification inspection for device classes N, Q, and V. Qualification inspection for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. Inspections to be performed sha

44、ll be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes N, Q, and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as

45、specified herein and the QM Plan. 4.4.1 Group A inspection. a. Group A testing is not required if all tests have been performed during final electrical of the 100% Screening test. See footnote 7/ for table IIA. b. Subgroup 4 (capacitance measurements) shall be measured only for initial qualification

46、 and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 5 devices with no failures, and all input and output terminals tested. c. For device Classes N, Q, and V, subgroups 7 and 8 shall include verifying the functionality of the device. Provi