DLA SMD-5962-04220 REV D-2012 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 1 000 000 GATES MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added case outline U, and updated associated paragraphs and figures. Added note 6 to section 1.3 and renumbered existing. Updated lead solder temperature in section 1.3. Added note to section 1.6.3. Updated figure in Table I footnote 10. ksr 07-0

2、4-23 Robert M. Heber B Add device types 05 through 08 to section 1.2.2; add and edit footnote designations in section 1.2.2 and the corresponding footnotes at bottom of page 2. Made additional changes in paragraphs for inclusion of devices 05 through 08 where applicable. Added new test in 4.4.1.f.(4

3、) for thermal runaway. Made changes to Table I where applicable, also corrected figure in footnote 6/ of Table I. ksr 08-03-12 Robert M. Heber C Change maximum Input voltage (VI) in section 1.3 from 3.75 V to 4.1 V max, change Maximum junction temperature (TJ) from 125 oC to 135oC, and update footno

4、te 10/. Make changes to Table I; clarifications for 5 V tolerance, standby currents, and I/O related changes. Edit notes 2, 3, and 8 on Figure 2; and add note 10. ksr 09-08-17 Charles F. Saffle D Updated devices for class V. Updated footnote information for 1.2.4. Updated 2.2. Added and resequenced

5、footnotes in Table I. Added binning circuit delay test in Table I. Deleted “and Table IIA note 8/ herein” from Table I footnote 1/. Deleted “Qualification inspection for all devices (01 to 08) complies with class Q level requirements only.” from 4.3. Updated 4.4.2.2. Updated Table IIA and footnotes.

6、 Updated Table IIB. Removed vendor website URL from 6.7. Updated boilerplate to current requirements. lhl 12-03-09 Charles F. Saffle REV D D SHEET 35 36 REV D D D D D D D D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV D D D D D D D D D D D

7、D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Raymond Monnin MICR

8、OCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 1,000,000 GATES, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 06-04-20 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-04220 SHEET 1 OF 36 DSCC FORM 2233 APR 97 5962-E234-12 Provid

9、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04220 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance

10、class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are

11、reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 04220 01 Q X C | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2

12、.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appro

13、priate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 RTAX1000S 1,000,000 gate field programmable gate array 02 RTAX1000S-1 1,000,000 gate field programmable gate

14、 array 1/ 03 RTAX1000S 1,000,000 gate field programmable gate array 2/ 04 RTAX1000S-1 1,000,000 gate field programmable gate array 1/ 3/ 05 RTAX1000SL 1,000,000 gate field programmable gate array 4/ 06 RTAX1000SL-1 1,000,000 gate field programmable gate array 1/ 4/ 07 RTAX1000SL 1,000,000 gate field

15、 programmable gate array 4/ 5/ 08 RTAX1000SL-1 1,000,000 gate field programmable gate array 1/ 4/ 6/ Note: These devices are specified at junction operating temperature and not at case operating temperature. 1.2.3 Device class designator. The device class designator is a single letter identifying th

16、e product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2

17、.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 352 Ceramic Quad Flat Pack Y See figure 1 624 Ceramic Land Grid Array (LGA) Z See figure 1 624 Ceramic Column Grid Array (CGA) 7/ U S

18、ee figure 1 624 Ceramic Column Grid Array (CGA) 7/ 1/ Timing performance of the RTAX1000S-1 and RTAX1000SL-1 devices shall be approximately 15% faster than the RTAX1000S and RTAX1000SL devices respectively (End users may select the appropriate device speed grade through timing calculations based on

19、timing simulation of specific designs with manufacturers Libero/Designer software, see 6.7 herein). 2/ Device type 03 is device type 01 with additional testing (see 4.2.2.f). Device type 03 is only offered as a Class Q device. 3/ Device type 04 is device type 02 with additional testing (see 4.2.2.f)

20、. Device type 04 is only offered as a Class Q device. 4/ Silicon used for all devices are the same silicon, at 125oC final electrical test, device type 05 to 08 is screened to a lower ICCAlimit (see Table I herein) 5/ Device type 07 is device type 05 with additional testing (see 4.2.2.f). Device typ

21、e 07 is only offered as a Class Q device. 6/ Device type 08 is device type 06 with additional testing (see 4.2.2.f). Device type 08 is only offered as a Class Q device. 7/ Case outline U has a different solder composition than Z (see Figure 1 for details). Provided by IHSNot for ResaleNo reproductio

22、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04220 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-

23、PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings (for 1.5V/1.8V/2.5V/3.3V operating conditions). 8/ DC core supply voltage (VCCA) . -0.3 to +1.7 V DC I/O supply voltage (VCCI) -0.3 to +3.75 V DC supply voltage for differential I/Os (VCCDA) -0.3 to +3.75 V DC I/O reference volta

24、ge (VREF) . -0.3 to +3.75 V DC external pump supply voltage (VPUMP) . -0.3 to +3.75 V Input voltage (VI) . -0.5 to +4.1 V 9/ Output voltage (VO) . -0.5 to +3.75 V Storage temperature range (VSTG) . -65oC to +150oC Lead temperature (soldering, 10 seconds) X . 300oC Y, Z, and U . 245C Maximum junction

25、 temperature (TJ) 135oC 10/ Thermal resistance, junction-to-case (JC): Case outline X 0.4oC/W 11/ 14/ Case outline Y 5.7oC/W 12/ 14/ Case outlines Z and U 5.6oC/W 12/ 14/ Thermal resistance, junction-to-board (JB) for case outline Z and U 4.5oC/W 13/ 14/ AC core supply transient voltage (VCCA) -0.3

26、to +1.8 V 15/ 1.4 Recommended operating conditions. 1.5V core supply voltage . 1.425 to 1.575 V dc 1.5V I/O supply voltage . 1.425 to 1.575 V dc 1.8V I/O supply voltage . 1.71 to 1.89 V dc 2.5V I/O supply voltage . 2.375 to 2.625 V dc 3.3V I/O supply voltage . 3.0 to 3.6 V dc 2.5V VCCDAI/O supply vo

27、ltage (no differential I/O used) . 2.375 to 2.625 V dc 3.3V VCCDAI/O supply voltage (differential or voltage referenced I/O used) . 3.0 to 3.6 V dc 3.3V VPUMPsupply voltage range 3.0 to 3.6 V dc Junction operating temperature range (TJ) . -55oC to +125oC 8/ Stresses above the absolute maximum rating

28、 may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 9/ Overshoot/Undershoot limits: For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer than 10% of the period or 11 ns whichever is

29、smaller. Current during the transition must not exceed 95 mA. For AC signals, the input signal may overshoot during transitions to VCCI+ 1.0 V for no longer than 10% of the period or 11 ns whichever is smaller. Current during the transition must not exceed 95 mA. Note: This specification does not ap

30、ply to the PCI standard. The PCI I/Os of this device are compliant to the PCI standard including the PCI overshoot/undershoot specifications. 10/ Maximum junction temperature shall not be exceeded except for allowable short durations during burn-in screening conditions in accordance with method 5004

31、 of MIL-STD-883. TJ=135oC applies with wafer lot numbers starting with D2xxxx. For older wafer lot numbers starting with D1xxxx, the TJ=125oC still applies. 11/ JCfor case outline X refers to the thermal resistance between the junction and the bottom of the package. 12/ JCfor case outlines Y, Z, and

32、 U refers to the thermal resistance between the junction and the top of the package (surface of the metal lid). 13/ JBfor case outlines Z and U refers to the thermal resistance between the junction and the tips of the solder columns (where the device is attached to the circuit board) 14/ All thermal

33、 resistance data are obtained through simulation with computational fluid dynamic software. For case outlines Z and U, the JBis simulated with 4L/2P SMT board per JEDEC Standard No. 51. 15/ AC transient VCCAlimit is for radiation induced transients less than 10s duration, and not intended for repeti

34、tive use. Core voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the transient does not exceed 1.8 V at any time, and the total time that the transient exceeds 1.575 V does not exceed 10 s in duration.Provided by

35、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-04220 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 1.5 Power-Up/Down Sequence. All device I/Os are tri-stated during power

36、-up until normal device operating conditions are reached, which is when I/Os enter user mode. VCCA, VCCI, and VCCDAcan be powered up or powered down in any sequence. All device I/Os are hot-swap compliant with cold-sparing support (except PCI). 1.5.1 R-cells and I/O Registers. On a chip-wide basis a

37、t power-up, all R-cells and I/O Registers are either cleared or preset by driving the global clear (GCLR) and global preset (GPSET) inputs (see Figure 3). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. 1.6 Device Logic Configuration. 1.6.1 Core array logics inc

38、lude two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). C-cell contains carry logic for efficient arithmetic functions. R-cell appears as a single D-type flip-flop to user, but is implemented in silicon with triple module redundancy (TMR) to improve SEU perfo

39、rmance. Each TMR R-cell consist of three master-slave latch pairs, each with asynchronous self-correcting feedback paths. Output of the TMR R-cell is the result of the majority voting of the outputs of the three flip flops in the TMR R-cells. Logic modules are grouped as SuperCluster, each SuperClus

40、ter has two Clusters, and each Cluster includes two C-cells, one R-cell, two transmit (TX) and two receive (RX) routing buffers. Each SuperCluster also includes an independent buffer module. On the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip.

41、There are nine core tiles in this device and each tile has 336 SuperClusters, resulting a total of 6,048 R-cells and 12,096 C-cells in the device. 1.6.2 Clock Resources are available with two types of global clock networks throughout the chip. There are four dedicated hardwired clock input pins (HCL

42、KA/B/C/D) that will directly drive all the sequential modules (R-cells, I/O registers, embedded RAM/FIFO). There are also four global clock input pins (CLKE/F/G/H) for routed clock distribution networks that are buffered prior to clocking the R-cells; the routed clocks can also be programmed to driv

43、e S0, S1, PSET, and CLR of a register, or as the inputs of any C-cell. Input levels for all clocks are compatible with all supported I/O standards (there is a P/N pin pair to support differential I/O standards). All clock networks have been hardened to improve SEU performance. 1.6.3 Embedded RAM is

44、available as a global resource. There are four 4,608-bit RAM blocks in each tile, with a total of 165,888 bits in the device. Each 4,608-bit RAM block can be organized as 128x36, 256x18, 512x9, 1,024x4, 2,048x2, or 4,096 x1 (Depth x Word in bits), and are cascadable to create larger memory sizes. Ea

45、ch RAM block has independent read and write ports, which enables simultaneous read and write operations; it also contains its own embedded FIFO controller, allowing the RAM blocks to be configured as either RAM or FIFO. SRAM structures are susceptible to radiation upsets, to achieve high level SEU p

46、erformance, manufacturer has provided an IP core to enhance the SEU tolerance of the embedded RAM blocks by mitigating upsets with Error Detection and Correction (EDAC) and background memory-refresher (or scrubber). Registers in the FIFO controller are not hardened for radiation, so when high SEU to

47、lerance is required, the FIFO control unit should be implemented with core logic. Note: Simultaneous read and write operations to the same address is not supported. 1.6.4 Multi-Standard I/Os are available on all I/O pins. Below table shows all supported I/O standards. Each I/O provides programmable

48、slew rates, drive strength, and weak pull-up and pull-down circuits (in the order of 10k), it also includes three registers (input (InReg), output (OutReg), and enable (EnReg). I/Os are organized into eight banks (0-7) with two banks per device side. Each I/O bank has a common VCCIand a common refer

49、ence-voltage bus. For each I/O bank, multiple I/O standards may be selected, however, all I/O standards used in the same I/O bank shall have the same VCCIvalue and the same VREFvalue (when required). VREFpin is not pre-defined, any user I/O in the bank can be selected to be a VREF. I/O Standard Input/Output Supply Voltage (VCCI) Input Reference