DLA SMD-5962-06233 REV B-2013 MICROCIRCUIT DIGITAL RADIATION HARDENED LOW VOLTAGE CMOS MINIMUM SKEW ONE-TO-EIGHT CLOCK DRIVER LVTTL COMPATIBLE INPUTS AND OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change IDDQin table IA. Add a footnote to table IA for VOLand VOH. Change limits in table IIB. - jak 07-07-19 Thomas M. Hess B Add die for device types 01 and 02 with die appendix A. Update radiation features in section 1.5 and add footnote 3/ fo

2、r the device type 02. Delete class M requirements. - MAA 13-01-08 Thomas M. Hess REV SHEET REV B B B B B B B SHEET 15 16 17 18 19 20 21 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHI

3、O 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles F. Saffle THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, RADIATION HARDENED, LOW VOLTAGE CMOS, MINIMUM SKEW ONE-TO-EIGHT CLOCK DRIVER, LVTTL COMPATI

4、BLE INPUTS AND OUTPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 07-03-28 AMSC N/A REVISION LEVEL B SIZE CAGE CODE 67268 5962-06233 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E461-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without

5、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space

6、application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 59

7、62 H 06233 01 V X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specifi

8、ed RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the

9、 circuit function as follows: Device type Generic number Circuit function 01 54ALVC2525 Minimum skew, one-to-eight clock driver, LVTTL compatible inputs and outputs 02 54ALVC2525 Minimum skew, one-to-eight clock driver, LVTTL compatible inputs and outputs 1.2.3 Device class designator. The device cl

10、ass designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Des

11、criptive designator Terminals Package style X See figure 1 14 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. . Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI

12、ZE A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Core power supply voltage range (VDD) . -0.3 V dc to +4.0 V dc Any clock input voltage range (VIN) -0.3 V dc to VDD+ 0.3 V dc Any clock output voltage range

13、 (VOUT) . -0.3 V dc to VDD+ 0.3 V dc DC input current (II) . 10 mA Maximum power dissipation (PD) . 1000 mW Storage temperature range (TSTG) . -65C to +150C Maximum junction temperature (TJ) . +150C 2/ Lead temperature (soldering, 10 seconds) 260C Thermal resistance, junction-to-case (JC) . 20 C/W 1

14、.4 Recommended operating conditions. Core operating voltage range (VDD) . +2.0 V dc to +3.6 V dc Any clock input voltage range (VIN) +0.0 V dc to VDDAny clock output voltage range (VOUT) . +0.0 V dc to VDD Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features. Maximum total do

15、se available (Dose rate = 50 300 rad(Si)/s): Device type 01 1 Mrad(Si) Device type 02 (effective dose rate = 1 rad (Si)/s) 100 Krad(Si) 3/ Single event phenomenon (SEP): No SEL occurs at effective LET (see 4.4.4.5) . 111 MeV/( cm2/mg) 4/ 5/ No SEU occurs at on set LET (see 4.4.4.5) 66 MeV/( cm2/mg)

16、4/ 6/ (Saturated cross section=5.5 x 10-7cm2/device) No SEU occurs at on set LET (see 4.4.4.5) 52 MeV/( cm2/mg) 4/ 7/ (Saturated cross section=8.7 x 10-7cm2/device) Neutron irradiation 1 X 1014neutron/cm2 4/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. This

17、 is a stress rating only, and functional operation for the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and perfo

18、rmance. 2/ Maximum junction temperature may be increased to +175C during burn-in and steady state life tests. 3/ Device type 02 is irradiated at dose rate = 50 - 300 rad (Si)/s in accordance with MIL-STD-883, method 1019, condition A, and is guaranteed to a maximum total dose specified. The effectiv

19、e dose rate after extended room temperature anneal = 1 rad (Si)/s per MIL-STD-883, method 1019, condition A, section 3.11.2. The total dose specification for these devices only applies to the specified effective dose rate, or lower, environment. 4/ Limits are guaranteed by design or process but not

20、production tested unless specified by the customer through the purchase order or contract. 5/ Worse case temperature and voltage of TC= +125C, VDD= 3.6 V. 6/ TC= 25C, VDD= 3.0 V, 200 MHz. 7/ TC= 25C, VDD= 2.0 V, 200 MHz. Provided by IHSNot for ResaleNo reproduction or networking permitted without li

21、cense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form

22、 a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE

23、STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are avail

24、able online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise s

25、pecified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document are available online

26、at http:/www.astm.org/ or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA 19428-2959.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD20 Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS devices. JESD78 IC Latch-Up Test. (Cop

27、ies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, th

28、e text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF

29、-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimension

30、s shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as spec

31、ified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.2.3 Logic diagram. The logic diagram s

32、hall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and

33、 shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in tab

34、le IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN l

35、isted in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designato

36、r shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as r

37、equired in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be

38、required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product mee

39、ts, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for Resale

40、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125

41、C +2.0 V VDD +3.6 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level input voltage VIHVDD= 2.0 V 1, 2, 3 All 1.25 V VDD= 2.75 V All 1.5 VDD= 3.0 V All 1.75 VDD= 3.6 V All 2.0 Low level input voltage VILVDD= 2.0 V 1, 2, 3 All 0.7 VDD= 2.75 V All 0.8 VDD= 3.0 V A

42、ll 0.8 VDD= 3.6 V All 0.8 Low Level output voltage VOLIOL= +12 mA, VDD= 2.0 V 1, 2, 3 01 0.45 V IOL= +12 mA, VDD= 2.75 V 1, 2, 3 01 0.4 IOL= +12 mA, VDD= 3.0 V 1, 2, 3 01 0.4 IOL= +12 mA, VDD= 3.6 V 1, 2, 3 01 0.4 VOL2/ IOL= +12 mA, VDD= 2.0 V 1, 2, 3 02 0.45 V IOL= +12 mA, VDD= 2.75 V 1, 2, 3 02 0.

43、4 IOL= +12 mA, VDD= 3.0 V 1, 2, 3 02 0.4 IOL= +12 mA, VDD= 3.6 V 1, 2, 3 02 0.4 High level output voltage VOHIOH= -12 mA, VDD= 2.0 V 1, 2, 3 01 1.5 V IOH= -12 mA, VDD= 2.75 V 1, 2, 3 01 2.2 IOH= -12 mA, VDD= 3.0 V 1, 2, 3 01 2.4 IOH= -12 mA, VDD= 3.6 V 1, 2, 3 01 3.0 VOH2/ IOH= -12 mA, VDD= 2.0 V 1,

44、 2, 3 02 1.5 V IOH= -12 mA, VDD= 2.75 V 1, 2, 3 02 2.2 IOH= -12 mA, VDD= 3.0 V 1, 2, 3 02 2.4 IOH= -12 mA, VDD= 3.6 V 1, 2, 3 02 3.0 Short circuit output current IOS3/ VOUT= VDDand VSS, VDD= 2.0 V 1, 2, 3 All -200 200 mA VOUT= VDDand VSS, VDD= 3.6 V 1, 2, 3 All -300 300 Input leakage current IILVIN=

45、 VDDor VSS, VDD= 3.6 V 1, 2, 3 All -1 +1 A Quiescent supply current IDDQVDD= 2.0 V 1, 2, 3 All 1.0 mA VDD= 3.6 V 1, 2, 3 All 1.0 Total power dissipation PD4/ VDD= 2.0 V, CL= 20 pF 1, 2, 3 All 1.2 mW/ MHZ VDD= 2.75 V, CL= 20 pF All 2.7 VDD= 3.0 V, CL= 20 pF All 3.5 VDD= 3.6 V, CL= 20 pF All 5.2 Input

46、 capacitance CINf = 1 MHz VDD= 0 V 4 All 15 pF Output capacitance COUTf = 1 MHz VDD= 0 V 4 All 15 pF Functional tests See 4.4.1b 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZ

47、E A 5962-06233 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C +2.0 V VDD +3.6 V unless otherwise specified Group A subgroups Device type Limits Unit M

48、in Max Propagation delay time, high-to-low, CLK to On tPHL5/ Measured as transition time between VIN= VDD/2 to VOUT= VDD/2 VDD= 2.0 V 1, 2, 3 All 3.5 7.5 ns VDD= 2.75 V All 3.0 5.5 VDD= 3.0 V All 2.75 5.25 VDD= 3.6 V All 2.25 4.75 Propagation delay time, low-to-high, CLK to On tPLH5/ Measured as transition time between VIN= VDD/2 to VOUT= VDD/2 VDD= 2.0 V 9, 10, 11 All 3.25 7.25 ns VDD= 2.75 V 2.75 5.25 VDD= 3.0 V 2.5 5.0 VDD= 3.6 V 2.0 4.5 Maximum skew, common edge, output-to-output, high-to-low transition tOSHL5/, 6/ VDD= 2.0 V 9, 10, 11 All 0.15 ns VDD= 3