DLA SMD-5962-08202 REV C-2013 MICROCIRCUIT MEMORY DIGITAL CMOS SOI 2M x 8-BIT RADIATIONHARDENED LOW VOLTAGE SRAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Made changes to Table IA, parameters: IDDDOP3, IDDDOP1, IDDDOPW1, IDDOPW40, IDDDOPW40, IDDOPR1, IDDDOPR1, IDDOPR40, IDDDOPR40, CINA, CINC. ksr 08-12-12 Robert M. Heber B Made changes to Table IA, parameters: Standby current CS disabled (IDDSB2),

2、from 25mA to 30 mA, and Standby current enabled ( IDDSB) from 25 mA to 30 mA. ksr 09-07-17 Charles Saffle C Added device type 02 a 1.5 V capable device. Updated boilerplate to current MIL-PRF-38535 requirements and removed all class M references. Correct Figure 4 test circuit and max junction temper

3、ature TJ from 150C to 175C in 1.3. Made editorial changes to sections 1.2.2, 1.4, 1.6, Table 1A and Table 1B, Table IIB. lht 13-06-12 Charles Saffle REV SHEET REV C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12

4、13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Cheri Rida THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Robert M. Heber MICROCIRCUIT, MEMORY, DIGITAL, CMOS/SOI, 2M x 8-B

5、IT, RADIATION-HARDENED, LOW VOLTAGE SRAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 08-07-08 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-08202 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E343-13 Provided by IHSNot for ResaleNo reproduction or networkin

6、g permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device

7、 class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN shall be as shown in

8、the following example: 5962 H 08202 01 Q X C Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet

9、the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 1/ HXSR01608-A(Q or V)H 2M

10、 X 8-bit rad-hard CMOS/SOI SRAM 20 ns 02 1/ HLXSR01608-A(Q or V)H 2M X 8-bit rad-hard CMOS/SOI SRAM 25 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certif

11、ication and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 40 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 f

12、or device classes Q and V _ 1/ See Table IA for conditions that clarify access times. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHE

13、ET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range I/O (VDDD) . -0.5 V dc to +4.4 V dc Supply voltage range Core (VDD) -0.5 V dc to +2.4 V dc DC input voltage range (VIN) . -0.5 V dc to VDDD+ 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VDDD+ 0.5 V dc DC or a

14、verage output current (IOUT) 15 mA Storage temperature . -65C to +150C Lead temperature (soldering 5 seconds) +270C Thermal resistance, junction to case (JC) . 2.0 C/W Output voltage applied to high Z-state -0.5 V dc to VDDD+ 0.5V dc Maximum power dissipation . 2.5 W Case operating temperature range

15、 (TC) . -55C to +125C Maximum junction temperature (TJ) 175C 1.4 Recommended operating conditions. 4/ Supply voltage range I/O (VDDD) . 3.0 V dc to 3.6 V dc Optional Supply voltage range I/O (VDDD)(Device type 01) 2.3 V dc to 2.7 V dc Supply voltage range Core (VDD) 1.65 V dc to 1.95 V dc Optional S

16、upply voltage range Core (VDD)(Device type 02) . 1.35 V dc to 1.65 V dc Supply voltage reference (VSS) . 0.0 V dc High level input voltage range (VIH) 0.7 x VDDDto VDDD+ 0.3 V dc Low level input voltage range (VIL) . -0.3 V dc to 0.3 x VDDD Voltage on any pin (VIN) -0.3 V dc to VDDD+ 0.3 Power Down

17、Time 5 ms minimum Power Up Ramp Time (VDDD http:/www.astm.org.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 78 - IC Latch-Up Test. (Copies of this document are available online at http:/www.jedec.org/ or from JEDEC, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201). (Non-Government

18、standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawin

19、g and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and

20、V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permit

21、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified i

22、n MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and Figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on Figure 2. 3.2.3 Truth table. The truth table shall be as specified on Figur

23、e 3. 3.2.4 Output load circuit. The output load circuit for functional tests shall be as specified on Figure 4. 3.2.5 Tester timing characteristics and timing waveforms. The tester AC timing characteristics and timing waveforms shall be as specified on Figure 5 and applies to capacitance, read cycle

24、, and write cycle measurements unless otherwise specified. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.2.7 Functional

25、 tests. Various functional tests used to test this device are contained in the appendix (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns

26、 shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise sp

27、ecified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II

28、A. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the man

29、ufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes

30、 Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of c

31、ompliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance

32、as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME

33、COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/ 2/ Test Symbol Conditions -55C TC+125C 3.0 V VDDD 3.6 V or 2.3 V VDDD 3.7 V and 1.65 V VDD 1.95 V unless otherwise specified Group A Sub-groups Device type Limits Unit Min Ma

34、x Device type 01 Standby Current NCS disabled IDDSB2 IDDDSB2 F=0MHz, NCS, NOE, NWE = VDDD1, 2, 3 01 30.0 0.3 mA Standby Current enabled IDDSB IDDDSB F=0MHz, NCS, NOE, NWE=VSS1, 2, 3 01 30.0 0.3 mA Operating Supply Current Disabled, address bus at max frequency 3/ IDDOP3 IDDDOP3F=40MHz, NCS, NOE, NWE

35、 = VDDD1, 2, 3 01 2 5 mA Operating Supply Current Deselected, write mode 3/ IDDOP1 IDDDOP1NCS, NOE = VDDD, 1MHz NWE vector controlled 1, 2, 3 01 0.1 0.2 mA Operating Supply Current Selected, write mode low frequency 3/ IDDOPW1 IDDDOPW1F=1MHz, NCS=VSS, NOE=VDDD, NWE vector controlled 1, 2, 3 01 2 0.2

36、 mA Operating Supply Current Selected, write mode high frequency 3/ IDDOPW40 IDDDOPW40F=40MHz, NCS=VSS, NOE=VDDD, NWE vector controlled 1, 2, 3 01 80 8.0 mA Operating Supply Current Selected, read mode low frequency 3/ IDDOPR1 IDDDOPR1F=1MHz, NCS=VSS, NOE, NWE =VDD1, 2, 3 01 1.0 0.2 mA Operating Sup

37、ply Current Selected, read mode high frequency 3/ IDDOPR40 IDDDOPR40F=40MHz, NCS=VSS, NOE, NWE =VDD1, 2, 3 01 40 8.0 mA Data Retention Current IDR1 IDR2VDD= 1.0 V VDDD= 2.0 V 1, 2, 3 01 20 0.2 mA Low level output voltage VOLVDDD= 3.0 V, VDD= 1.65 V, IOL=10mA, VIL =VSS, VIH = VDDD1, 2, 3 01 0.4 V Hig

38、h level output voltage VOHVDDD= 3.0 V, VDD=1.65 V, IOH=-5mA, VIL = VSS, VIH = VDDD1, 2, 3 01 2.7 V Input leakage current IILKVIN= 3.6 V, VDDD= 3.6 V, VDD= 1.95 V, all other pins at 3.6 V 1, 2, 3 01 5 A Output leakage current IOLKVOUT= 3.6V, VDDD= 3.6 V, VDD= 1.95 all other pins at 3.6 V 1, 2, 3 01 1

39、0 A Input capacitance 4/ (address and control) CINA CINC VIN= VDDDor VSS, f = 1 MHz See 4.4.1e 4 01 5 15 pF Output capacitance 4/ COUT4 01 7 pF Functional tests See 3.2.7 and 4.4.1.c 7, 8 01 Data retention voltage VDRVDDD= 2.0 V, VDD= 1.0 V 7, 8 01 5/ See footnotes at end of table. Provided by IHSNo

40、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. 1/ 2/ Test Sym

41、bol Conditions -55C TC+125C 3.0 V VDDD 3.6 V or 2.3 V VDDD 3.7 V and 1.65 V VDD 1.95 V VIH=VDDD, VIL=VSSunless otherwise specified Group A Sub-groups Device type Limits Unit Min Max Device type 01 Read cycle time tAVAVR3.0 V VDDD 3.6 V, 1.65 V VDD 1.95 V 2.3 V VDDD 2.7 V, 1.65 V VDD 1.95 V 9, 10, 11

42、 01 20 22 ns Address access time tAVQV3.0 V VDDD 3.6 V, 1.65 V VDD 1.95 V 2.3 V VDDD 2.7 V, 1.65 V VDD 1.95 V 9, 10, 11 01 20 22 ns Address change output invalid time tAXQX9, 10, 11 01 4 ns Chip select access time tSLQV3.0 V VDDD 3.6 V, 1.65 V VDD 1.95 V 2.3 V VDDD 2.7 V, 1.65 V VDD 1.95 V 9, 10, 11

43、 01 20 22 ns Chip select to output enable time tSLQX9, 10, 11 01 0 ns Chip select to output disable time tSHQZ9, 10, 11 01 4 ns Output enable access time tGLQV9, 10, 11 01 6 ns Output enable to output active time tGLQX9, 10, 11 01 0 ns Output enable to output disable time tGHQZ9, 10, 11 01 4 ns Writ

44、e cycle time tAVAVW9, 10, 11 01 12 ns Mininum write enable pulse width tWLWH9, 10, 11 01 7 ns Chip select to end of write time tSLWH9, 10, 11 01 10 ns Data valid to end of write time tDVWH9, 10, 11 01 6 ns Address valid to end of write time tAVWH9, 10, 11 01 12 ns Data hold time after end of write t

45、ime tWHDX9, 10, 11 01 0 ns Address valid setup to start of write time tAVWL9, 10, 11 01 0 ns Address valid hold after end of write time tWHAX9, 10, 11 01 0 ns Write enable to output disable time tWLQZ9, 10, 11 01 4 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or net

46、working permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. 1/ 2/ Test Symbol Conditions -55C TC+125C 3.0 V

47、VDDD 3.6 V or 2.3 V VDDD 2.7 V and 1.65 V VDD 1.95 V VIH=VDDD, VIL=VSSunless otherwise specified See figure 5 Group A sub-groups Device type Limits Unit Min Max Device type 01 Write disable to output enable time tWHQX9, 10, 11 01 0 ns Write disable write enable pulse width 6/ tWHWL9, 10, 11 01 5 ns

48、See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics - Continued. 1/ 2/ Test Symbol Conditions -55C