DLA SMD-5962-08203 REV D-2013 MICROCIRCUIT MEMORY DIGITAL CMOS SOI 512K X 32-BIT (16M) RADIATION-HARDENED LOW VOLTAGE SRAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Made changes to Table IA, parameters: IDDDOP3, IDDDOP1, IDDDOPW1, IDDOPW40, IDDDOPW40, IDDOPR1, IDDDOPR1, IDDOPR40, IDDDOPR40, CINA, CINC. Made change to Figure 2; terminal 83, changed from NC to VDD. ksr 08-12-12 Robert M. Heber B Made changes t

2、o Table IA, parameters: Standby current CS disabled (IDDSB2), from 25mA to 30 mA, and Standby current enabled (IDDSB) from 25 mA to 30 mA. Ksr 09-07-17 Charles F. Saffle C Added device type 02 a 1.5 V capable device. Made editorial changes to sections 1.2.2, 1.4, 1.6, Table 1A and Table 1B, and Appe

3、ndix B to accommodate the addition of device 02. Changed max junction temperature TJ from 150C to 175C. lhl 12-01-13 Charles F. Saffle D Corrected figure 4. Updated radiation features in section 1.6 and SEP Table IB. Updated drawing to current MIL-PRF-38535. lht 13-06-14 Charles F. Saffle REV SHEET

4、REV D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWI

5、NG CHECKED BY Cheri Rida THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Robert M. Heber MICROCIRCUIT, MEMORY, DIGITAL, CMOS/SOI, 512K X 32-BIT (16M), RADIATION-HARDENED, LOW VOLTAGE SRAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 08-07-08 AM

6、SC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-08203 SHEET 1 OF 25 DSCC FORM 2233 APR 97 5962-E334-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990

7、 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the P

8、art or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H 08203 01 Q X C Federal RHA Device Device Case Lead stock class designator type class outline finish des

9、ignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devic

10、e. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 1/ HXSR01632-D(Q or V)H 512K X 32-bit rad-hard CMOS/SOI SRAM 1MRAD 20 ns 02 1/ HLXSR01632-D(Q or V)H 512K X 32-bit rad-hard CMOS/SOI SRAM 1MRAD 25 ns 1.2

11、.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designate

12、d in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 86 Flat pack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V or MIL-PRF-38535. _ 1/ See Table IA for conditions that clarify access times. Prov

13、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range I/O (V

14、DDD) . -0.5 V dc to +4.4 V dc Supply voltage range Core (VDD) -0.5 V dc to +2.4 V dc DC input voltage range (VIN) . -0.5 V dc to VDDD + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VDDD + 0.5 V dc DC or average output current (IOUT) 15 mA Storage temperature . -65C to +150C Lead temperature

15、(soldering 5 seconds) +270C Thermal resistance, junction to case (JC) . 2.5C/W Output voltage applied to high Z-state -0.5 V dc to VDDD + 0.5V dc Maximum power dissipation . 2.5 W Case operating temperature range (TC) -55C to +125C Maximum junction temperature (TJ) 175C 1.4 Recommended operating con

16、ditions. 4/ Supply voltage range I/O (VDDD) . 3.0 V dc to 3.6 V dc Optional Supply voltage range I/O (VDDD) (Device type 01) . 2.3 V dc to 2.7 V dc Supply voltage range Core (VDD) (Device type 01) 1.65 V dc to 1.95 V dc Optional Supply voltage range Core (VDD) (Device type 02) 1.35 V dc to 1.65 V dc

17、 Supply voltage reference (VSS) . 0.0 V dc High level input voltage range (VIH) 0.7 x VDDD to VDDD + 0.3 V dc Low level input voltage range (VIL) . -0.3 V dc to 0.3 x VDDD Voltage on any pin (VIN) -0.3 V dc to VDDD + 0.3 Power Down Time 5 ms minimum Case operating temperature range (TC) . -55C to +1

18、25C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) 100 percent 1.6 Radiation features. 5/ For device types 01 and 02: Maximum total dose available (dose rate = 50-300 rad (Si)/s)1 Mrads(Si) Single event phenome

19、non (SEP) (see 4.4.4.4): Heavy ion No SEL at an effective LET 120 MeV-cm2/mg Heavy Ion Single event upset (SEU) rate 1 x 10-12 upsets/bit-day 6/ Proton Single event upset (SEU) rate for device type 01 . 2 x 10-12 upsets/bit-day 6/ Proton Single event upset (SEU) rate for device type 02 .5 x 10-12 up

20、sets/bit-day 6/ Neutron irradiation 1 x 1014 neutrons/cm2 7/ Dose rate induced upset 1 x 1010 Rad(Si)/sec for 50 nsec Dose rate survivability 1 x 1012 Rad(Si)/sec for 50 nsec Latch-up Immune by SOI technology 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Ext

21、ended operation at the maximum levels may degrade performance and affect reliability. 3/ All voltages are referenced to VSS. 4/ Maximum applied voltage shall not exceed 4.4 V. 5/ For details RHA parameters and test results, contact the device manufacturer. 6/ Projected performance based on CREME96 r

22、esults for a geosynchronous orbit during solar minimum non-flare conditions behind 100mil Aluminum shield using Weibull parameters derived from actual test data (see 4.4.4.4). Weibull parameters are available from the vendor to calculate projected upset rates for other orbits/environments (such as A

23、dams 90% worst case) and using different upset rate calculating programs (such as Space Radiation 5.0). 7/ Guaranteed but not tested for 1MeV equivalent neutrons. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59

24、62-08203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Un

25、less otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits

26、. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil/ or from the Stan

27、dardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the docume

28、nts cited in the solicitation. ASTM INTERNATIONAL (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Bo

29、x C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201).

30、 (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the te

31、xt of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for devi

32、ce classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.1.1 Microcircuit die. For the requirements

33、of microcircuit die, see Appendix B to this document. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2 D

34、esign, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and Figure 1. 3.2.2 Terminal connections. The te

35、rminal connections shall be as specified on Figure 2. 3.2.3 Truth table. The truth table shall be as specified on Figure 3. 3.2.4 Output load circuit. The output load circuit for functional tests shall be as specified on Figure 4. 3.2.5 Tester timing characteristics and timing waveforms. The tester

36、AC timing characteristics and timing waveforms shall be as specified on Figure 5 and applies to capacitance, read cycle, and write cycle measurements unless otherwise specified. 3.2.6 Radiation exposure circuit. The radiation test circuit shall be maintained under document revision level control by

37、the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.7 Functional tests. Various functional tests used to test this device are contained in the appendix (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate

38、test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity

39、upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature rang

40、e. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be

41、 marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall b

42、e in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 l

43、isted manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q

44、and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networ

45、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08203 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/ 2/ Test Symbol Conditions -55C TC +125C 3.0 V VDDD 3.6 V or

46、2.3 V VDDD 2.7 V and 1.65 V VDD 1.95 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Device type 01 Standby Current NCS disabled IDDSB2 F=0MHz, NCS, NOE, NWE = VDDD 1, 2, 3 01 30.0 mA IDDDSB2 0.3 Standby Current enabled IDDSB F=0MHz, NCS, NOE, NWE=VSS 1, 2, 3 01 30.0 I

47、DDDSB 0.3 Operating Supply Current Disabled, address bus at max frequency 3/ IDDOP3 F=40MHz, NCS, NOE, NWE = VDDD 1, 2, 3 01 2 IDDDOP3 5 Operating Supply Current Deselected, write mode 3/ IDDOP1 NCS, NOE = VDDD, 1MHz NWE vector controlled 1, 2, 3 01 0.1 IDDDOP1 0.15 Operating Supply Current Selected

48、, write mode low frequency 3/ IDDOPW1 F=1MHz, NCS=VSS, NOE=VDDD, NWE vector controlled 1, 2, 3 01 5.0 IDDDOPW1 0.35 Operating Supply Current Selected, write mode high frequency 3/ IDDOPW40 F=40MHz, NCS=VSS, NOE=VDDD, NWE vector controlled 1, 2, 3 01 200 IDDDOPW40 14.0 Operating Supply Current Selected, read mode low frequen