DLA SMD-5962-08215 REV B-2013 MICROCIRCUIT MEMORY DIGITAL CMOS SOI 512K X 8-BIT (4M) RADIATION-HARDENED LOW VOLTAGE SRAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to Table IA parameters IDDDOP3 from 3 mA to 4 mA, IDDOPW1 from 1 mA to 1.25 mA, IDDOPR1 from .6 mA to .75 mA, IDDDOP3_VR from 4 mA to 5 mA, IDDDOPW1_VR from 1 mA to 1.25 mA, and IDDDOPR1_VR from .6 mA to .75 mA. ksr 09-07-17 Charles Saffl

2、e B Add device type 02. Updated boilerplate to current MIL-PRF-38535 requirements. Removed all class M references. Corrected JC from 2.05 C/W to 2.0 C/W and TJ from 150C to 175C in 1.3. Decimal place correction in Figure 1, b dimensions (millimeters column). Modified Delta column and added IDDDSBVR0

3、2 parameters in Table IIB. lht 13-05-06 Charles Saffle REV SHEET REV B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/

4、www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Cheri Rida THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Robert M. Heber MICROCIRCUIT, MEMORY, DIGITAL, CMOS/SOI, 512K X 8-BIT (4M), RADIATION-HARDENED, LOW VOLTAGE SRAM, MONOLITHIC SILICON AND AGENCIES OF THE DE

5、PARTMENT OF DEFENSE DRAWING APPROVAL DATE 08-10-14 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-08215 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E325-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

6、08215 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lea

7、d finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H 08215 01 Q X C Federal RHA Device Device Case Lead st

8、ock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desi

9、gnator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 HXS6408 512K X 8-bit CMOS/SOI SRAM 15 ns 02 HRT6408 512K X 8-bit CMOS/SOI SRAM 15 ns 1.2.3 Device class desig

10、nator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and a

11、s follows: Outline letter Descriptive designator Terminals Package style X See figure 1 36 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAND

12、ARD MICROCIRCUIT DRAWING SIZE A 5962-08215 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range I/O (VDDD) . -0.5 V dc to +4.4 V dc Supply voltage range Core (VDD) -0.5 V dc to +2.4 V dc DC input volta

13、ge range (VIN) . -0.5 V dc to VDDD + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VDDD + 0.5 V dc DC or average output current (IOUT) 15 mA Storage temperature . -65C to +150C Lead temperature (soldering 5 seconds) +270C Thermal resistance, junction to case (JC) . 2.0 C/W Output voltage appl

14、ied to high Z-state -0.5 V dc to VDDD + 0.5V dc Maximum power dissipation 0.7 W Case operating temperature range (TC) -55C to +125C Maximum junction temperature (TJ) 175C 1.4 Recommended operating conditions. 3/ Supply voltage range I/O (VDDD) . 3.0 V dc to 3.6 V dc Optional Supply voltage range I/O

15、 (VDDD) 2.3 V dc to 2.7 V dc Supply voltage range Core (VDD) 1.65 V dc to 1.95 V dc 4/ Supply voltage reference (VSS) . 0.0 V dc High level input voltage range (VIH) 0.7 x VDDD to VDDD + 0.3 V dc Low level input voltage range (VIL) -0.3 V dc to 0.3 x VDDD Voltage on any pin (VIN) -0.3 V dc to VDDD +

16、 0.3 Power Down Time 100 s Case operating temperature range (TC) . -55C to +125C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) 100 percent 1.6 Radiation features. 5/ Maximum total dose available (dose rate = 5

17、0 rad(Si)/s): Device type 01. 1x 106 Rads(Si) Device type 02. 3x 105 Rads(Si) Maximum total dose available (dose rate = 300 rad/s X-ray source) Device type 01. 1 x 106 Rads(Si) Device type 02. 3 x 105 Rads(Si) Single event phenomenon (SEP) (see 4.4.4.4): Heavy ion No SEL at an effective LET. 120 MeV

18、-cm2/mg Heavy Ion Single event upset (SEU) rate 1 x 10-12 upsets/bit-day 6/ Proton Single event upset (SEU) rate. 2 x 10-12 upsets/bit-day 6/ Neutron irradiation 1 x 1014 neutrons/cm2 7/ Dose rate induced upset for device type 01 1 x 1010 Rad(Si)/sec for 50 nsec Dose rate survivability for device ty

19、pe 01 1 x 1012 Rad(Si)/sec for 50 nsec Latch-up . Immune by SOI technology 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages are referenced to VSS. 3/ Maximu

20、m applied voltage shall not exceed 4.4 V. 4/ Optional on die Voltage Regulator allows device operation without VDD core supply. 5/ For details RHA parameters and test results, contact the device manufacturer. 6/ Projected performance based on CREME96 results for a geosynchronous orbit during solar m

21、inimum non-flare conditions behind 100mil Aluminum shield using Weibull parameters derived from actual test data (see 4.4.4.4). Weibull parameters are available from the vendor to calculate projected upset rates for other orbits/environments (such as Adams 90% worst case) and using different upset r

22、ate calculating programs (such as Space Radiation 5.0). 7/ Guaranteed but not tested for 1MeV equivalent neutrons. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08215 DLA LAND AND MARITIME COLUMBUS, OHIO 43

23、218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these do

24、cuments are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic C

25、omponent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Aven

26、ue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ASTM INTERNATIONAL

27、 ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 194

28、28-2959; http:/www.astm.org.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 78 - IC Latch-Up Test. (Copies of this document are available online at http:/www.jedec.org/ or from JEDEC, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). (Non-Government standards and other publications

29、are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein

30、, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SI

31、ZE A 5962-08215 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the devic

32、e manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for de

33、vice classes Q and V 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and Figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on Figure 2. 3.2.3 Truth table. The truth table shall be as specified on Figure 3. 3.2.4 Output load circuit. Th

34、e output load circuit for functional tests shall be as specified on Figure 4. 3.2.5 Tester timing characteristics and timing waveforms. The tester AC timing characteristics and timing waveforms shall be as specified on Figure 5 and applies to capacitance, read cycle, and write cycle measurements unl

35、ess otherwise specified. 3.2.6 Radiation exposure circuit. The radiation test circuit shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.7 Functional tests. Various functional tests used t

36、o test this device are contained in appendix A (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns shall be under the control of the device

37、 manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performanc

38、e characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup

39、 are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking t

40、he “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as requi

41、red in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Marit

42、ime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in

43、 MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08215 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL

44、B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. 1/ 2/ Test Symbol Conditions -55C TC +125C 3.0 V VDDD 3.6 V 1.65 V VDD 1.95 V unless otherwise specified 3/ Group A Sub-groups Device type Limits Unit Min Max Standby Current NCS disabled, regulator disabled Checkerboa

45、rd pattern IDDSB2 IDDDSB2 f = 0 MHz, NVREN, NCS, NOE, NWE, Address, Data = VDDD; VDDD = 3.6 V, VDD = 1.95 V 1, 2, 3 All 12.0 0.2 mA Standby Current enabled, regulator disabled Complement Checkerboard pattern IDDSB8 IDDDSB8 f = 0 MHz, NVREN = VDDD, NCS, NWE, NOE , Address, Data = VSS, VDDD = 3.6 V, V

46、DD = 1.95 V 1, 2, 3 All 12.0 0.2 mA Operating Supply Current Disabled, regulator disabled, 4/ IDDOP3 IDDDOP3 f = 40 MHz, NVREN, NCS, NOE, NWE = VDDD, VDDD = 3.6 V, VDD = 1.95 V, address switching 4, 5, 6 All 1.0 4.0 mA Operating Supply Current Deselected, regulator disabled, write mode 4/ IDDOP1 IDD

47、DOP1 f = 1 MHz, NVREN, NCS, NOE = VDDD, NWE vector controlled, VDDD = 3.6 V, VDD = 1.95 V, address and data switching 4, 5, 6 All 0.1 0.1 mA Operating Supply Current Selected, regulator disabled, write mode low frequency 4/ IDDOPW1 IDDDOPW1 f = 1 MHz, NCS=VSS, NVREN, NOE=VDDD, NWE vector controlled,

48、 VDDD = 3.6 V, VDD = 1.95 V, address and data switching 4, 5, 6 All 1.25 0.15 mA Operating Supply Current Selected, regulator disabled, write mode high frequency 4/ IDDOPW50 IDDDOPW50 f = 50 MHz, NCS=VSS, NVREN, NOE=VDDD, NWE vector controlled, VDDD = 3.6 V, VDD = 1.95 V, address and data switching 4, 5, 6 All 50 7.5 mA Operating Su