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本文(DLA SMD-5962-08220-2009 MICROCIRCUIT MEMORY DIGITAL CMOS 1M X 16 (16M) 3 3 V STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf)为本站会员(figureissue185)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-08220-2009 MICROCIRCUIT MEMORY DIGITAL CMOS 1M X 16 (16M) 3 3 V STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice STANDARD MICROCIRCUIT DRAWING CHECKED BY Cheri Rida DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 htt

2、p:/www.dscc.dla.mil APPROVED BY Robert M. Heber THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 09-01-21 MICROCIRCUIT, MEMORY, DIGITAL, CMOS 1M X 16 (16M) 3.3 V, STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AMSC N/A REVIS

3、ION LEVEL SIZE A CAGE CODE 67268 5962-08220 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E203-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVI

4、SION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Pa

5、rt or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 08220 01 M X A | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator ty

6、pe class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M

7、RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Data

8、 retention Access time 01 1M X 16 CMOS SRAM Yes 12 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compl

9、iant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X

10、See figure 1 54 SO flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document an

11、d will also be listed in MIL-HDBK-103 (see 6.6.2 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 A

12、PR 97 1.3 Absolute maximum ratings. 2/ Voltage on any input relative to VSS- -0.3 V dc to + 4.6 V dc Storage temperature range - -65C to +150C Maximum power dissipation (PD) - 0.58 W Lead temperature (soldering, 10 seconds) - +260C Thermal resistance, junction-to-case (JC): Case X - 7 C/W 3/ Junctio

13、n temperature (TJ) - +140C 4/ Output current - 20 mA 1.4 Recommended operating conditions. Supply voltage range (VCC) - 3.0 V dc to 3.6 V dc Supply voltage (VSS) - 0 V Input high voltage range (VIH) - 2.0 V dc to VCC+ 0.3 V dc Input low voltage range (VIL) - 0.3 V dc to + 0.8 V dc 5/ Case operating

14、temperature range (TC) - -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those

15、 cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Out

16、lines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue,

17、Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR T

18、ESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Co

19、nshohocken, PA 19428-2959; http:/www.astm.org.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Tested initially and after any design or process changes that may affe

20、ct these parameters. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ VIL(MIN) = -2.0 V dc and VIH(MAX) = VCC +2 V dc for pulse width less than 20 ns. Provided by IHSNot for Resale

21、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up

22、Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. The

23、se documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes

24、applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Manag

25、ement (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construct

26、ion, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein

27、 and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix herein. If the te

28、st patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the p

29、reparing or acquiring activity upon request. For device classes Q and V alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 E

30、lectrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical te

31、st requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages

32、 where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with

33、MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as requi

34、red in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance s

35、hall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for d

36、evice classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFEN

37、SE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Units Test Symbol Conditions -55C TC 125C 3.0 V VCC 3.6 V Unless Otherwise Specified Group A Subgroups Device Type Min Max Output HIGH Voltage VOH

38、VCC = Min., IOH = -4.0 mA 1, 2, 3 01 2.4 V Output LOW Voltage VOLVCC = Min., IOL = 8.0 mA 1, 2, 3 01 0.4 V Input Leakage Current ILKGND VI VCC1, 2, 3 01 -1 +1 uA Output Leakage Current IOLKGND VOUT VCC,Output Disabled 1, 2, 3 01 -1 +1 uA VCCOperating Supply Current ICCVCC= MAX f = fMAX = 1/tRC1, 2,

39、3 01 175 mA Automatic CE Power-Down Current TTL Inputs ISB1MAX VCC, VIH VIN VIH or VIN VILf = fMAX1, 2, 3 01 35 mA Automatic CE Power-Down-CMOS Inputs ISB2MAX VCC, VCC 0.3 V, VIN VCC 0.3 V, or VIN 0.3 V, f=0 1, 2, 3 01 35 mA Input Capacitance 1/ CIN TA= 25C, f = 1 MHz, VCC = 3.3 V 4 01 8 pF Input /O

40、utput Capacitance 1/ COUTTA= 25C, f = 1 MHz, VCC= 3.3 V 4 01 10 pF VCCfor Data Retention VDR2/ 1, 2, 3 01 2.0 V Data Retention Current ICCDRVCC= VDR= 2.0 V VCC 0.3 V VIN VCC- 0.3 V or VIN 0.3 V 2/ 1, 2, 3 01 25 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network

41、ing permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. See footnotes at end of table. Limits Units Te

42、st Symbol Conditions -55C TC 125C 3.0 V VCC 3.6 V Unless Otherwise Specified Group A Subgroups Device Type Min Max Read Cycle Time tRC9, 10, 11 01 12 ns Address to Data Valid tAA9, 10, 11 01 12 ns Data Hold from Address Change tOHA 9, 10, 11 01 3 ns LOW to Data Valid tACE9, 10, 11 01 12 ns LOW to Da

43、ta Valid tDOE9, 10, 11 01 6 ns LOW to Low Z 5/ 6/ tLZOE 9, 10, 11 01 1 ns HIGH to High Z 5/ 6/ 7/ tHZOE 9, 10, 11 01 6 ns LOW to Low Z 5/ 6/ tLZCE 9, 10, 11 01 3 ns HIGH to High Z 5/ 6/ 7/ tHZCE9, 10, 11 01 6 ns Byte Enable to Data Valid tDBE 9, 10, 11 01 6 ns Byte Enable to Low Z 5/ 6/ tLZBE 9, 10,

44、 11 01 1 ns Byte Disable to High Z 5/ 6/ 7/ tHZBE 9, 10, 11 01 6 ns Write Cycle Time 8/ 9/ tWC9, 10, 11 01 12 ns LOW to Write End tSCE9, 10, 11 01 7 ns Address Set-Up to Write End tAW9, 10, 11 01 7 ns Address Hold from Write End tHA9, 10, 11 01 0 ns Address Set-Up to Write Start tSASee figure 5 as a

45、pplicable. 3/ 4/ 9, 10, 11 01 0 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-08220 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electric

46、al performance characteristics - Continued. Limits Units Test Symbol Conditions -55C TC 125C 3.0 V VCC 3.6 V Unless Otherwise Specified Group A Subgroups Device Type Min Max Pulse Width tPWE9, 10, 11 01 7 ns Data Set-Up to Write End 9/ tSD9, 10, 11 01 5.5 ns Data Hold from Write End tHD9, 10, 11 01 0 ns HIGH to Low Z 5/ 6/ 9/ tLZWE 9, 10, 11 01 3 ns LOW to High Z 5/ 6/ 7/ 9/ tHZWE 9, 10, 11 01 6 ns Byte Enable to End of Write tBW See figure 5 as applicable. 3/ 4/ 9, 10, 11 01 7 ns Chip Deselect to Data Retention

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