DLA SMD-5962-12219 REV A-2012 MICROCIRCUIT HYBRID LINEAR SINGLE CHANNEL DC-DC CONVERTER.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I: For VOUTLoad Regulation (VRLOAD) test, correct maximum value for device type “01” from “20” mV to “25” mV. Table I: For Input Current (IIN) test for IOUT= 0, Inhibit (pin 3) = open, delete extra row for device type “02” with max limit of

2、 40 mA. Table I: Correct conditions for Efficiency (Eff) test from “VOUT= 3.3 VVIN= 5 V, VOUT= 3.3 V IOUT= 10 A” to “VOUT= 3.3 V” -gc 12-12-11 Charles F. Saffle REV SHEET REV A SHEET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY G

3、reg Cecil DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Greg Cecil COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Charles F. Saffle MICROCIRCUIT, HYBRID, LINEAR, SINGLE CHANNEL, DC-DC CONVERTER AND AGENCI

4、ES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 12-06-28 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-12219 A SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E125-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

5、SIZE A 5962-12219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available

6、and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 12219 01 K X A Federal stock class designator RHA designator (see 1.2.1) Device typ

7、e (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A d

8、ash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 SVGA0510S DC-DC Converter, 33 W, 10 A Output 02 SVGA0515S DC-DC Converter, 50 W, 15 A Output 1.2.3 Device class designator. This devic

9、e class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Dev

10、ice class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing ver

11、sion of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D

12、). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s)

13、 taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

14、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminal

15、s Package style X See figure 1 9 Dual-in-line 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Input Voltage (Continuous) . 7 V dc Input Voltage (Transient, 1 second) 7.5 V dc Power Dissipation (PD, Full Load, TCASE= +125C) . 7.5 W Output Po

16、wer (Dependent on Output Voltage): Device type 01 . 33 W Device type 02 50 W Junction Temperature Rise to Case . +11 C Storage Temperature -65 C to +150 C Lead Solder Temperature (10 seconds) . +270 C 1.4 Recommended operating conditions. Input Voltage Range +4.2 V dc to +7 V dc Output Voltage Range

17、 . +0.8 V dc to +3.4 V dc Case Operating Temperature Range (TC) . -55 C to +125 C 1.5 Radiation features. Maximum total dose available (dose rate = 30 - 300 rads(Si)/s) 100 krads(Si) 2/ Maximum total dose available (dose rate 10 mrads(Si)/s) LDR: 100 krads(Si) 2/ Neutron Irradiation (1 MeV equivalen

18、t neutrons) . 1x1012n/cm23/ No Single event phenomenon (SEP) effective linear energy transfer (LET): SEL, SEB, SEGR, SEFI (Destructive) 90 nm X (100 krads) X (100 krads) X X (hybrid level test) (N) (N) (N) X (1x1012) Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

19、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 13 DSCC FORM 2234 APR 97 Table IIIB. Hybrid level and element level test table. Continued. NOTES: X = Radiation Testing Done Level X(100K) = Level in rad(Si) X(1x1012

20、) = Level in n/cm2G = Device Mfr Guaranteed (QML-V or Class S) (N) = Not yet tested N/A = Not Applicable P = Program-Specific testing 4.3.5.1 Radiation Hardness Assurance (RHA) inspection. RHA qualification is required for those devices with the RHA designator as specified herein. End-point electric

21、al parameters for radiation hardness assurance (RHA) devices shall be specified in table II. Radiation testing will be in accordance with the qualifying activity (DLA Land and Maritime-VQ) approved plan and with MIL-PRF-38534, Appendix G. a. The hybrid device manufacturer shall establish procedures

22、controlling element radiation testing, and shall establish radiation test plans used to implement element lot qualification during procurement. Test plans and test reports shall be filed and controlled in accordance with the manufacturers configuration management system. b. The hybrid device manufac

23、turer shall designate a RHA program manager to oversee element lot qualification, and to monitor design changes for continued compliance to RHA requirements. c. As an alternative to element level testing, elements may be procured to manufacturer radiation testing that meet the minimum performance re

24、quirements. Element radiation performance testing shall be established in compliance with MIL-PRF-19500, Group D or MIL-PRF-38535, Group E, as applicable. VPT SVGA Radiation Test SMD 5962-12219 Prompt Dose Hybrid Level Testing DRU (upset) DRL (latch) Parametric (survive) (N) (N) (N) Element Level Te

25、sting CMOS Discrete (Power MOSFET) (N) (N) (N) Bipolar Discrete Devices (N) (N) (N) Bipolar Linear or Mixed Signal 90 nm (N) (N) (N) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12219 DLA LAND AND MARITIME

26、 COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 14 DSCC FORM 2234 APR 97 4.3.5.1.1 Hybrid level radiation qualification. 4.3.5.1.1.1 Qualification by similarity. A family is defined by the family model designator e.g. SVGA single/dual. All parts with this designator share a common design and use t

27、he same active elements. Device type 5962R1221901KXA was tested and all other devices on this SMD are qualified by similarity. 4.3.5.1.1.2 Total ionizing dose irradiation testing. A minimum of one representative hybrid of the hybrid family (family model designator, e.g. SVGA Single) is characterized

28、 and tested initially and after any design or process changes which may affect the RHA response of the device type. Devices are tested at High Dose Rate (HDR) in accordance with condition C (dose rate of 30-300 rads(Si)/s) and at Low Dose Rate (LDR) in accordance with condition D of method 1019 of M

29、IL-STD-883 to 100 krads(Si). The sample size will consist of a minimum of 1 biased sample for HDR and LDR and 1 unbiased sample for HDR and LDR. These sample sizes are not sufficient to meet the procedures to determine if the devices exhibit low dose rate effects (ELDRS) per paragraph 3.13.1.1, of m

30、ethod 1019 of MIL-STD-883. 4.3.5.1.1.3 Single event phenomena (SEP). A minimum of one representative hybrid of the hybrid family is characterized for SEE response at initial qualification and after any design or process changes which may affect the RHA response of the device type. Testing shall be p

31、erformed in accordance with ASTM F1192. Test conditions for SEP are as follows: a. The ion beam angle of incidence shall be normal to the die surface. No shadowing of the ion beam due to fixturing is allowed. b. The fluence shall be 1x107 particles/cm2. c. The flux shall be between 102and 105ions/cm

32、2/s. d. The particle range shall be 35 micron in silicon. e. The characterization is performed at nominal input voltage, and with both minimum and maximum load. The test temperature shall be +25C 10 C in air, except latch-up which is at +125C 10 C in air. f. For SEP test limits, see table IB herein.

33、 4.3.5.1.2 Element level radiation qualification 4.3.5.1.2.1 Technologies not being tested. Testing is not performed on device technologies including: Junction Diodes, Schottky and zener diodes that the manufacturer determines to be radiation hardened. 4.3.5.1.2.2 Total Ionizing Dose Irradiation. Te

34、sting every initial wafer lot of bipolar / BiCMOS linear or mixed signal semiconductor elements will be characterized and tested at HDR in accordance with condition C (dose rate of 30-300 rads(Si)/s) of method 1019 of MIL-STD-883. Bipolar linear integrated circuits elements will be characterized and

35、 tested at LDR in accordance with condition D of method 1019 or MIL-STD-883. The data will be analyzed in accordance with condition D of method 1019 of MIL-STD-883, to determine if the elements exhibit low dose rate effects (ELDRS). A minimum of 10 samples for HDR (5 biased and 5 unbiased), and 10 s

36、amples for LDR (5 biased and 5 unbiased) will be tested. If a specific element type is determined to exhibit ELDRS, all wafer lots of that specific element will be tested at LDR. 4.3.5.1.2.3 Neutron Irradiation. Every initial wafer lot of bipolar linear or mixed signal integrated circuit and semicon

37、ductor elements will be tested to minimum average integrated neutron fluence (1 MeV SI equivalent) of 1 x 1012n/cm2in accordance with method 1017 of MIL-STD-883 using a minimum sample size of 5 devices. MIL-STD-883 method 1017 requires 10 samples. 4.3.5.2 Radiation lot Acceptance. Each lot of active

38、 elements shall be evaluated for acceptance in accordance with MIL-PRF-38534 and herein. 4.3.5.2.1 Total Ionizing Dose. Every wafer lot of bipolar / BiCMOS semiconductor elements will be RLAT (Radiation Lot Acceptance Testing) tested at HDR in accordance with condition C (dose rate of 30-300 rads(Si

39、)/s) of method 1019 of MIL-STD-883. A minimum of 5 biased samples and 5 unbiased samples will be tested. 0.9900/90% statistics are applied to the device parameter degradations which are compared against established limits for lot acceptance. Low dose rate will be used in lieu of HDR for parts that e

40、xhibit ELDRS effects or for which ELDRS evaluation per method 1019 MIL-STD-883 is not available.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12219 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION L

41、EVEL A SHEET 15 DSCC FORM 2234 APR 97 4.3.5.2.2 Neutron Irradiation. Every wafer lot of bipolar linear or mixed signal integrated circuit and semiconductor elements will be tested to minimum average integrated neutron fluence (1 MeV SI equivalent) of 1 x 1012n/cm2 in accordance with method 1017 of M

42、IL-STD-883 using a minimum sample size of 5 devices. MIL-STD-883 method 1017 requires 10 samples. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for us

43、e for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configuration control of SMDs. A

44、ll proposed changes to existing SMDs will be coordinated as specified in MIL-PRF-38534. 6.4 Record of users. Military and industrial users shall inform DLA Land and Maritime when a system application requires configuration control and the applicable SMD. DLA Land and Maritime will maintain a record

45、of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-0547. 6.5 Comments. Comments on this drawing should be directed to DLA Land and

46、 Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-1081. 6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103 and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DLA Land and Maritime-VA and have a

47、greed to this drawing. 6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Occurrence of latchup (SEP). d Occurrence of Burn-out (SEP). e. Occurrence of

48、Gate Rupture (SEP). f. Functional Interrupt (SEP). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 12-12-11 Approved sources of supply for SMD 5962-12219 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepte