DLA SMD-5962-12229-2012 MICROCIRCUIT DIGITAL CMOS MICROPROCESSOR WITH DECOUPLING CAPACITORS SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIR

2、CUIT DRAWING CHECKED BY Phu H. Nguyen THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, CMOS, MICROPROCESSOR WITH DECOUPLING CAPACITORS, SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 12-07-16 AMSC N/A REVISION LEVEL SIZE

3、A CAGE CODE 67268 5962-12229 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E413-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12229 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC

4、FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number

5、 (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 12229 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (

6、see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A speci

7、fied RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 8447257-1244 192 MHz microprocessor 02 8447257-1234 200 MHz mic

8、roprocessor 03 8447257-1334 200 MHz microprocessor 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 complian

9、t, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See

10、 figure 1 255 Ceramic column grid array with thermal epoxy 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

11、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12229 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Core and PLL supply voltage range (VDD) -0.4 V dc to +2.4 V dc 60X Bus supply voltage range (OVDD) -0.6 V dc to +4.2 V dc

12、DC input voltage range (VIN) . -0.6 V dc to +4.2 V dc Maximum power dissipation at (PD): Device type 01 5.3 W Device type 02 5.0 W Device type 03 5.7 W Storage temperature range (TSTG) -65C to +150C Lead temperature (soldering, 45 seconds, maximum +180C) +220C Thermal resistance, junction-to-column

13、(JB) 1.5C/W 3/ 1.4 Recommended operating conditions. 4/ 5/ Core supply voltage range (VDD): Device types 01 and 02 . +1.710 V dc to +1.890 V dc Device type 03 . +1.805 V dc to +1.995 V dc 60x Bus supply voltage range (OVDD) . +3.0 V dc to +3.6 V dc Logic low input voltage range (VIL) GND to 0.8 V dc

14、 System clock input high voltage (CVIH) . 2.0 V dc to 3.6 V dc System clock input low voltage (CVIL) . GND to 0.4 V dc Minimum high level output voltage (VOH) 2.4 V dc Maximum low level output voltage (VOL) . 0.4 V dc Frequency of operation (fOP): Device type 01 192 MHz Device types 02 and 03 200 MH

15、z Case operating temperature range (TC) -55C to +125C 1.5 Radiation features. Maximum total dose available (dose rate = 50-300 rads(Si)/s) . 1 Mrad (Si) Single event phenomenon (SEP) effective linear energy threshold (LET) with no latchup 120 MeV-cm2/mg 6/ Single event upset (SEU) 1 x 10-10 upsets/b

16、it-day 6/ Neutron irradiation 1 x 1012neutrons/cm26/ Prompt dose upset (RPRU) 1 x 109rad(Si)/sec 6/ Dose rate survivability (RS) 1 x 1011rad(Si)/sec 6/ _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade perfo

17、rmance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ Value is theoretical, JBmounted to an infinite heatsink. This value assumes 5 W maximum power. 4/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temp

18、erature range of -55C to +125C unless otherwise noted. 5/ Power sequencing: Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents. Power-up sequence: GND, OVDD, VDD, Inputs Power-down sequence: Inputs, VDD, OVDD, GND All power sequencing is

19、subject to limits in paragraph 1.3. The sequencing of VDD, OVDD, and can be modified as long as all requirements of notes X and Y are met. The loss of the 1.8 V power supply (3.3 V power supply active) coupled with an external event (e.g. SEU hit on a critical I/O circuit) may result in a shorting c

20、ondition. This combined event cannot exist for more than 10 seconds (cumulative time) without reliability impact. A safety margin is included in this analysis, contact the manufacturer is this limit has been exceeded. If there is no external event, the loss of the 1.8 V power supply alone will not r

21、esult in any reliability impact. 6/ Limits are guaranteed by design or process but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR

22、AWING SIZE A 5962-12229 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifi

23、ed herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. MIL-PRF-123 - Capacitors, Fixed, Ceramic dielectric, (Temperature S

24、table and General Purpose), High Reliability, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircui

25、t Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Go

26、vernment publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single

27、 Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document is available online at http:/www.astm.org or from ASTM International, P. O. Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959). IEEE - THE INSTITUTE OF ELECTRICAL AND ELECTRONIC

28、S ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. 2.3 Order of precedence. In the even

29、t of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individ

30、ual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual

31、item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein

32、 for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12229 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHE

33、ET 5 DSCC FORM 2234 APR 97 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing

34、waveforms. The timing waveforms shall be as specified on figures 4 and 5. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3

35、.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electric

36、al test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pac

37、kages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance

38、with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as

39、required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of complia

40、nce shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacture

41、rs product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for devi

42、ce class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this dr

43、awing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentatio

44、n. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). 3.11 IEEE 1149.1 compliance interf

45、ace. The boundary-scan interface of the device is a fully compliant implementation of the IEEE 1149.1 standard. 3.12 Internal decoupling capacitors. Discrete capacitor arrays are included under the lid of the package, but external to the die. Ceramic capacitors shall meet approved criteria (design,

46、screening, and testing) in accordance with MIL-PRF-123 or as approved by the qualifying activity. The capacitor arrays are included to improve the capability of the device and are an integral part of the package design. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

47、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-12229 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions 1/ +1.62 V VDD +1.995 V, +3.0 V OVDD +3.6 V, -55C TC +125C, unl

48、ess otherwise specified Device type Group A Subgroups Limits Unit Min Max Input high voltage (all Inputs except SYSCLK) VIHAll 1, 2, 3 2.0 3.6 V Input low voltage (all Inputs except SYSCLK) VILAll 1, 2, 3 0.0 0.8 SYSCLK input high voltage CVIHAll 1, 2, 3 2.0 3.6 V SYSCLK input low voltage CVILAll 1, 2, 3 0.0 0.4 SCAN IDDQlow voltage SCAN IDDQLOV TC= +25C VDDcore = 1.62 V, VDDI/O = 3.0 V, 80 ns, 001 LPAT, 004 Stop Addresses and Measurements All 1 - 250 mA M, D, P, L, R, F, G, H - 250 SCAN IDDQnominal voltage SCAN IDDQNOM TC= +25C VDDcore = 1.8 V, VDDI/O = 3.3 V, 80 ns, 001 LPAT, 0