DLA SMD-5962-84043 REV F-2011 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS EXCLUSIVE NOR GATE MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Add device type 02, convert to military drawing format, and inactivate for new design (device types 01AX and 01CX). Change code ident. no. to 67268. 87-08-27 N. A. Hauck D Update boilerplate to MIL-PRF-38535 requirements. - CFS 01-08-24 Thomas M.

2、 Hess E Made change to paragraph 3.5. Update boilerplate to MIL-PRF-38535 requirements. - LTG 05-03-17 Thomas M. Hess F Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-07-26 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV F F F F F F F F F F

3、OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D.

4、 A. DiCenzo APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, EXCLUSIVE NOR GATE, MONOLITHIC SILICON DRAWING APPROVAL DATE 84-05-09 REVISION LEVEL F SIZE A CAGE CODE 14933 84043 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E443-11 Provided by IHSNot for ResaleNo reproduction or networking

5、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircui

6、ts in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84043 01 C A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circui

7、t function as follows: Device type Generic number Circuit function 01 54HC266 Quad 2-input exclusive NOR gate (open drain output) 02 54HC7266 Quad 2-input exclusive NOR gate 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive design

8、ator Terminals Package style A GDFP5-F14 or CDFP6-F14 14 Flat pack B GDFP4-F14 14 Flat packC GDIP1-T14 or CDIP2-T14 14 Dual-in-lineD GDFP1-F14 or CDFP2-F14 14 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Ab

9、solute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current. 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA S

10、torage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 5/ _ 1/ Stresses above the absolute maximum rating may cause permanen

11、t damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature r

12、ange of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networki

13、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +2.0 V dc to +6.0 V dc Case operating temperature

14、 range (TC) . -55C to +125C Input rise or fall time: VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the ex

15、tent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Meth

16、od Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps

17、.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of thes

18、e documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC

19、 Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes

20、 applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that

21、is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in

22、 accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QM

23、L“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-399

24、0 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2

25、Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and te

26、st circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The el

27、ectrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufactu

28、rers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certific

29、ation mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compli

30、ance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PR

31、F-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and

32、 Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted withou

33、t license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Device type Group A

34、 subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= -20 A VCC=2.0 V 02 1, 2, 3 1.9 V VCC=4.5 V 4.4 VCC=6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC=4.5 V 3.7 VIN= VIHor VILIOH= -5.2 mA VCC=6.0 V 5.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC=2.0 V All 1, 2, 3 0.1

35、 V VCC=4.5 V 0.1 VCC=6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC=4.5 V 0.4 VIN= VIHor VILIOL= +5.2 mA VCC=6.0 V 0.4 High level input voltage VIH2/ VCC=2.0 V All 1, 2, 3 1.5 V VCC=4.5 V 3.15 VCC=6.0 V 4.2 Low level input voltage VIL2/ VCC=2.0 V All 1, 2, 3 0.3 V VCC=4.5 V 0.9 VCC=6.0 V 1.2 Input capacit

36、ance CINVIN= 0.0 V, TC = +25C See 4.3.1c All 4 10 pF Quiescent supply current ICCVCC= 6.0 V VIN= VCCor GND All 1, 2, 3 40 A Input leakage current IINVCC= 6.0 V VIN= VCCor GND All 1, 2, 3 1.0 A High level output current IOHVIN= VIHor VILVOUT= VCCVCC=6.0 V 01 1, 2, 3 10 A Functional tests See 4.3.1d A

37、ll 7 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performa

38、nce characteristics - Continued. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Device type Group A subgroups Limits Unit Min Max Propagation delay time, input to output, high-to-low, low-to-high tPHL, tPLH3/ TC= +25C CL= 50 pF 10% See figure 4 VCC=2.0 V All 9 125 ns VCC=4.5

39、V 25 VCC=6.0 V 21 TC= -55C and +125C CL= 50 pF 10% See figure 4 VCC=2.0 V All 10, 11 190 ns VCC=4.5 V 38 VCC=6.0 V 32 Transition time high-to-low, low-to-high tTHL, tTLH4/ TC= +25C CL= 50 pF 10% See figure 4 VCC=2.0 V All 9 75 ns VCC=4.5 V 15 VCC=6.0 V 13 TC= -55C and +125C CL= 50 pF 10% See figure

40、4 VCC=2.0 V All 10, 11 110 ns VCC=4.5 V 22 VCC=6.0 V 19 1/ For a power supply of 5 V 10% the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIH

41、value at 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage, and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 20 pF, determines the no load dynamic power consumption, PD= CPDVCC2+ ICCVCC, and the no load dyn

42、amic current consumption, IS= CPDVCCf + ICC. 2/ VIHand VILtests are not required if they are applied as forcing functions for the VOHand VOLtests. 3/ Propagation delay times, when VCC= 2.0 V and 6.0 V shall be guaranteed, if not tested, to the specified parameters. 4/ Transition time (tTHL, tTLH), i

43、f not tested, shall be guaranteed to the specified parameters. For device type 01, tTHLonly. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F S

44、HEET 7 DSCC FORM 2234 APR 97 Device types 01 and 02 Case outlines A, B, C, and D 2 Terminal number Terminal symbol 1 1A NC2 1B 1A 3 1Y 1B 4 2Y 1Y 5 2A NC 6 2B 2Y 7 GND NC 8 3A 2A 9 3B 2B 10 3Y GND 11 4Y NC 12 4A 3A 13 4B 3B 14 VCC3Y 15 NC 16 4Y 17 NC 18 4A 19 4B 20 VCCNC = No internal connection FIG

45、URE 1. Terminal connections. Device types 01 and 02 Inputs Outputs mA mB mY L L H L H L H L L H H H H = High voltage level L = Low voltage level FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

46、 A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. NOTES: 1. CL= 50 pF minimum or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to VCC; PRR 1MHz; ZO= 50; tr = 6.0 ns

47、; tf= 6.0 ns; trand tfshall be measured from 0.1 VCCto 0.9 VCC and from 0.9 VCC to 0.1 VCC, respectively; duty cycle = 50 percent. 3. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 4. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Swit

48、ching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84043 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices