DLA SMD-5962-84068 REV E-2005 MICROCIRCUIT DIGITAL CMOS CLOCK GENERATOR DRIVER MONOLITHIC SILICON《硅单片时钟发生驱动器 氧化物半导体数字微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Revise table I conditions. Make editorial changes. 85-11-15 M. A. Frye B Convert to military drawing format. Changes to 1.3 and 1.4. Changes to table I. Vendor CAGE 34649 added. Editorial changes throughout. 87-05-21 M. A. Frye C Remove vendor CA

2、GE 34649 from device 01. Add device 02. Changes to absolute maximum ratings. Change drawing CAGE. Editorial changes throughout. 88-04-08 M. A. Frye D Update boilerplate to MIL-PRF-38535 requirements. Update vendor CAGE 34371 information. Correct drawing title. - CFS 03-04-18 Thomas M. Hess E Correct

3、 marking requirements in 3.5. Update boilerplate in accordance with MIL-PRF-38535 requirements. - PHN. 05-03-17 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D D D SHEET 15 16 17 18 REV STATUS REV E D E E D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7

4、8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael. A. Frye AND AGENCIES OF THE DEPARTMENT OF

5、 DEFENSE DRAWING APPROVAL DATE 84-11-26 MICROCIRCUIT, DIGITAL, CMOS, CLOCK GENERATOR DRIVER, MONOLITHIC SILICON SIZE A CAGE CODE 67268 84068 AMSC N/A REVISION LEVEL E SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E243-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license

6、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance

7、 with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84068 01 V X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as

8、 follows: Device type Generic number Frequency Circuit function 01 82C84A 25 MHz Clock generator driver 02 82C84A 25 MHz Clock generator driver 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style V

9、 GDIP1-T18 or CDIP2-T18 18 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier X 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage (referenced to ground) . +8.0 V dc maximum Storage temperature range -65C to +150C Input

10、, output, or I/O voltage applied . GND -0.5 V dc to VCC +0.5 V dc Maximum power dissipation (PD) 1 W Lead temperature (soldering, 10 seconds). +275C Junction temperature (TJ) . +150C Thermal resistance, junction-to-case (JC): Cases V and 2 See MIL-STD-1835 1.4 Recommended operating conditions. Suppl

11、y voltage (VCC). +4.5 V dc to +5.5 V dc Frequency of operation. 25 MHz maximum Case operating temperature range (TC) . -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLU

12、MBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified,

13、the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface

14、 Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil o

15、r from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, ho

16、wever, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to t

17、his drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying act

18、ivity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described her

19、ein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1

20、Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 2. 3.2.4 Waveforms and test circuits. The waveforms and test c

21、ircuits shall be as specified on figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3.3 Electric

22、al performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifie

23、d in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/complianc

24、e mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certifi

25、cate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manu

26、facturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of cha

27、nge. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be

28、made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 T

29、ABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Input high voltage VIH VCC = 5.5 V 1/ 2/ 1, 2, 3 All 2.2 V Input low voltage VIL VCC = 4.5 V 1/ 2/ 3/ 1, 2, 3 All 0.8 V Output high voltag

30、e VOH IOH = -4.0 mA CLK output IOH = -2.5 mA all others VCC = 4.5 V 4/ 1, 2, 3 All VCC0.4 V Output low voltage VOL IOL = +4.0 mA CLK output IOL = +2.5 mA all others VCC = 4.5 V 4/ 1, 2, 3 All 0.4 V Reset input high voltage VIHR VCC = 5.5 V 1, 2, 3 All VCC0.8 V Reset input low voltage VILR VCC = 4.5

31、V 1, 2, 3 All 0.5 V 01 0.2 VCC V Reset input hysteresis VT+ - VT- VCC = 4.5 V and 5.5 V 1, 2, 3 02 100 mV Input leakage current IIL VIN = 0 V or VCC, does not include ASYNC, X1 VCC = 5.5 V 5/ 1, 2, 3 All -1.0 1.0 A Power supply current ICC VCC = 5.5 V Crystal outputs open 6/ 1, 2, 3 All 40 mA Input

32、capacitance CIN 4 All 10 pF Output capacitance COUT Frequency = 1 MHz TC = +25C VCC = GND = 0 V VIN = +5 V or GND See 4.3.1c 4 All 15 pF Functional tests See 4.3.1d 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,

33、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C VCC = +4.5 V unless otherwise specified Group A subg

34、roups Device type Limits Unit 7/ 8/ 9/ Min Max External frequency HIGH time tEHEL See figure 3. See Reference No. 1 10/ 90% - 90% VIN 11/ 9, 10, 11 All 13 ns External frequency LOW time tELEH See figure 3. See Reference No. 2 10/ 10% - 10% VIN 11/ 9, 10, 11 All 13 ns EFI period tELEL See figure 3. S

35、ee Reference No. 3 10/ 11/ 9, 10, 11 All 36 ns XTAL frequency 12/ All 2.4 25 MHz RDY1, RDY2 active setup to CLK tR1VCL See figure 3. See Reference No. 4 10/ ASYNC = HIGH 11/ 9, 10, 11 All 35 ns RDY1, RDY2 active setup to CLK tR1VCH See figure 3. See Reference No. 5 10/ ASYNC = LOW 11/ 9, 10, 11 All

36、35 ns RDY1, RDY2 inactive setup to CLK tR1VCL See figure 3. See Reference No. 4 10/ 9, 10, 11 All 35 ns RDY1, RDY2 hold to CLK tCLR1X See figure 3. See Reference No. 6 10/ 11/ 9, 10, 11 All 0 ns ASYNC setup to CLK tAYVCL See figure 3. See Reference No. 7 10/ 9, 10, 11 All 50 ns ASYNC hold to CLK tCL

37、AYX See figure 3. See Reference No. 8 10/ 9, 10, 11 All 0 ns AEN1, AEN2 setup to RDY1, RDY2 tA1VR1V See figure 3. See Reference No. 9 10/ 9, 10, 11 All 15 ns AEN1, AEN2 hold to CLK tCLA1X See figure 3. See Reference No. 10 10/ 11/ 9, 10, 11 All 0 ns See footnotes at end of table. Provided by IHSNot

38、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol C

39、onditions -55C TC +125C VCC = +4.5 V unless otherwise specified Group A subgroups Device type Limits Unit 7/ 8/ 9/ Min Max CSYNC setup to EFI tYHEH See figure 3. See Reference No. 11 10/ 9, 10, 11 All 20 ns CSYNC hold to EFI tEHYL See figure 3. See Reference No. 12 10/ 9, 10, 11 All 20 ns CSYNC widt

40、h tYHYL See figure 3. See Reference No. 13 10/ 11/ 9, 10, 11 All 2tELEL ns RES setup to CLK tI1HCL See figure 3. See Reference No. 14 10/ 13/ 9, 10, 11 All 65 ns RES hold to CLK tCLI1H See figure 3. See Reference No. 15 10/ 11/ 13/ 9, 10, 11 All 20 ns CLK cycle period tCLCL See figure 3. See Referen

41、ce No. 16 10/ 11/ 9, 10, 11 All 125 ns CLK HIGH time tCHCL See figure 3. See Reference No. 17 10/ 11/ 9, 10, 11 All (1/3tCLCL) + 2.0 ns CLK LOW time tCLCH See figure 3. See Reference No. 18 10/ 11/ 9, 10, 11 All (2/3tCLCL) - 15 ns PCLK HIGH time tPHPL See figure 3. See Reference No. 19 10/ 11/ 9, 10

42、, 11 All tCLCL - 20 ns PCLK LOW time tPLPH See figure 3. See Reference No. 20 10/ 11/ 9, 10, 11 All tCLCL - 20 ns Ready inactive to CLK 14/ tRYLCL See figure 3. See Reference No. 21 10/ 11/ 9, 10, 11 All -8 ns Ready active to CLK 15/ tRYHCH See figure 3. See Reference No. 22 10/ 11/ 9, 10, 11 All (2

43、/3tCLCL) - 15 ns CLK to reset delay tCLIL See figure 3. See Reference No.23 10/ 9, 10, 11 All 40 ns CLK to PCLK HIGH delay tCLPH See figure 3. See Reference No.24 10/ 9, 10, 11 All 22 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

44、se from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84068 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C VCC = +4.5 V unless otherwise specified

45、 Group A subgroups Device type Limits Unit 7/ 8/ 9/ Min Max CLK to PCLK LOW delay tCLPL See figure 3. See Reference No. 25 10/ 9, 10, 11 All 22 ns OSC to CLK HIGH delay tOLCH See figure 3. See Reference No. 26 10/ 11/ 9, 10, 11 All -5 22 ns OSC to CLK LOW delay tOLCL See figure 3. See Reference No.

46、27 10/ 11/ 9, 10, 11 All 2 35 ns CLK rise or fall time tCH1CH2, tCL2CL1 See figure 3. See Reference No. 28 10/ +1.0 V to +3.5 V 11/ 9, 10, 11 All 10 ns 1/ F/C pin is a strap option and should be held either 0.8 V or 2.2 V. Does not apply to X1 or X2 pin. 2/ Due to test equipment limitations related

47、to noise, the actual tested value may differ from that specified, but the specified limit is guaranteed. 3/ CSYNC pin is tested with VIL 0.8 V. 4/ Interchanging of force and sense conditions are permitted. 5/ ASYNC pin includes an internal 17.5 k nominal pull-up resistor. For ASYNC input at GND, ASY

48、NC input leakage current = 130 A nominal. X1 - Crystal feedback input. 6/ f = 25 MHz may be tested using the extrapolated value based on measurements taken at f = 2 MHz and f = 10 MHz. 7/ Unless otherwise specified, all timing delays are measured at 1.5 V. 8/ Input signals must switch between VIL (maximum) 0.4 V and VIH (minimum) + 0.4 V. RES and F/C must switch between 0.4 V and VCC 0.4 V. tr and tf typically equal to 1 ns/V. VIL VIL (maximum) 0.4 V for CSYNC pin. 9/ All ac parameters apply to device types 01 and 02 and are tested per AC