DLA SMD-5962-84111 REV F-2010 MICROCIRCUIT MEMORY DIGITAL 262 144-BIT (32K X 8) UV ERASEABLE PROM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Convert to military drawing format. Change drawing CAGE code to 67268. Add vendor CAGE 01295. Minor changes to table I and table II. Editorial changes throughout. Add device type 05 1987 OCT 13 M. A. Frye D Deleted CAGE 01295. Editorial changes t

2、hroughout. Made technical changes to table I, margin test method C (step 4), paragraph 4.3.1 (step C), table II, figure 5, paragraph 4.2, margin test method B (step 3), paragraph 1.2.2, paragraph 1.3, paragraph 1.4, figure 6, and table III. Added footnote 3, removed vendor name and address under ven

3、dor name and address, and added M38510/22403BYX to 8411104YX. 1989 JAN 11 M. A. Frye E Convert to newer standard boilerplate with the additional of QD requirement paragraphs. Changed maximum CIon table I from 6 pF to 10 pF and COfrom 12 pF to 15 pF. Changed subgroup 7 to 3 in Table II for Group C an

4、d D end-point electrical parameters. Updated boilerplate paragraphs. ksr 2004 NOV 08 Ray Monnin F Updated boilerplate paragraphs. glg 10-02-16 Charles Saffle The original first page of this drawing has been replaced. REV SHEET REV F SHEET 15 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET

5、 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve Duncan DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A Frye MICROCIRCUIT, MEMORY

6、 DIGITAL, 262,144-BIT (32K X 8) UV ERASEABLE PROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 18 October 1984 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 84111 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E052-10 Provided by IHSNot for ResaleNo reproduction o

7、r networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84111 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN cla

8、ss level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84111 01 X X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device ty

9、pe(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 27256-35 32K X 8-bit UV EPROM 350 ns 02 27256-25 32K X 8-bit UV EPROM 250 ns 03 27256-20 32K X 8-bit UV EPROM 200 ns 04 27256-17 32K X 8-bit UV EPROM 170 ns 05 27256-30 32K X 8-bit UV EPROM 300

10、 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Outline letter Descriptive designator Terminals Package style Y GDIP1-T28 or CDIP2-T28 28 dual-in-line package 1/ Z CQCC1-

11、N32 32 rectangular chip carrier package 1/ 1.3 Absolute maximum ratings. Supply voltage (VCC) 2/ . -0.6 V dc to +6.5 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) . 1.0 W Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-

12、STD-1835 Junction temperature (TJ) . +150C All input or output voltages with respect to ground -0.6 V dc to +6.5 V dc Voltage on pin A9with respect to ground . -0.6 V dc to +13.5 V dc VPPsupply voltage with respect to ground . -0.6 V dc to +13.0 V dc 1.4 Recommended operating conditions. Case operat

13、ing temperature range (TC) . -55C to +125C Input low voltage (VIL) . -0.1 V dc to +0.8 V dc Input high voltage (VIH) 2.0 V dc to VCC+1 V dc Supply voltage (VCC) . 4.5 V dc to 5.5 V dc High level program input voltage VIN(PR). 12.5 V dc 0.3 V dc (program method B) 1/ Lid shall be transparent to permi

14、t ultraviolet light erasure. 2/ All voltages referenced to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84111 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 223

15、4 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or

16、contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE H

17、ANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA

18、 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

19、3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified ma

20、nufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Manag

21、ement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify w

22、hen the QML flow option is used. (This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the qualifying activity.) 3.2 Design, construction, and physical dimensions. The design,

23、 construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Block diagram The block diagram shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table

24、(s) shall be as specified on figure 3. 3.2.4 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the f

25、ull case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part

26、 shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-” on the device. Provided by IHSNot fo

27、r ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84111 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be mar

28、ked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. (For product built in accordance with A.3.2.2 of MIL-PRF-3

29、8535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark.) 3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasu

30、re of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4 herein. 3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.6.3

31、Verification of erasure of programmability of EPROMS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that

32、 does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). Th

33、e certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in M

34、IL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.10 Verification and review. DSCC, DSCCs agent, and the acquiring activity r

35、etain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535

36、, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The tes

37、t circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent spe

38、cified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. A data retention stress test shall

39、 be included as part of the screening procedure and shall consist of the following steps: Margin test method A (1) Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.6.2). (2) Bake, unbiased, for 12 hours at +200C. Provided by IHSNot for ResaleNo repr

40、oduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84111 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 (3) Perform a margin test using Vm= VCC= 6.0 V at +25C using loose timing. (4) Erase device

41、, then program 45 to 50 percent of the bits to a worst case speed pattern. (5) Perform dynamic burn-in (see 4.2a). (6) Perform a margin test using Vm= VCC= 6.0 V at +25C. (7) Perform 100 percent electrical testing at +25C, +125C and -55C. (8) Erase device (see 3.6.1), except devices submitted for gr

42、oups A, B, C, and D. (9) Verify erasure (see 3.6.3). Margin test method B (1) Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.6.2). The remaining cells shall provide a worst case speed pattern. (2) Bake, unbiased, for 72 hours at +140C to screen fo

43、r data retention lifetime. (3) Perform a margin test using Vm= +6.0 V at +25C using loose timing (i.e., tAVQV= 1 s). (4) Perform dynamic burn-in (see 4.2a). (5) Margin at Vm= 6.0 V. (6) Perform electrical tests (see 4.2). (7) Erase (see 3.6.1), except devices submitted for groups A, B, C, and D test

44、ing. (8) Verify erasure (see 3.6.3). Margin test method C I. Wafer margin test method: (1) Program at +25C with a greater than 95 percent pattern, (example, all “0s“). (2) Measure VCCMAXand store in die signature row. (3) Unbiased bake for 2 hours at +250C. (4) Test at +25C. Measure VCCMAXand compar

45、e to VCCMAXstore in die. Any die with a delta greater than 0.66 V constitutes a failure and is removed from the lot. II. Back end margin test method: (1) Program at +25C with a greater than 95 percent pattern (example, all “0s“) (see 3.6.2). (2) Test at +25C (8.0 V), VCCMAXrange (6.0 V). Measure and

46、 record VCCMAXin signature row. (3) Unbiased bake for 32 hours at +200C. (4) Test at +25C (see I, step 4 above). (5) Erase (see 3.6.1). (6) Program at +25C with a 50 percent pattern (example checkerboard bar) (see 3.6.2). (7) Test at +25C (see 3.6.3) (8) Burn-in (see 4.2a). (9) Test at +25C (see 3.6

47、.3). (10) Test at +125C (see 3.6.3). (11) Test at -55C (see 3.6.3). (12) Erase (see 3.6.1). Devices may be submitted for groups A, B, C, and D testing at this point. (13) Verify erasure at +25C (see 3.6.3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

48、-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84111 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions Group A Device Unit -55C TC +125C subgroups type Min Max High level output VOHVCC= 5.50 V 1,2,3 All 2.4 V voltage IOH= -400 A Low level