DLA SMD-5962-84132 REV D-2011 MICROCIRCUIT MEMORY DIGITAL CMOS 16K STATIC RAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add six new device types 03-08. Add two new vendors CAGE 61772 and 65786 Editorial changes throughout. Convert to military drawing format. 87-10-15 R.P. Evans B Add vendor CAGE number 60911 to drawing as a supplier of the 05 device, packages “R“

2、and “Y“. Added a new device for vendor CAGE 61772. Changes to table I, figure 3, figure 5, table II and vendor similar part number in paragraph 6.4. Editorial changes throughout. Inactivate for new design device type 02RX. Add vendor CAGE 60911 to 02YX, 08YX, and 08RX. 88-09-13 M. A. Frye C Boilerpl

3、ate update, part of 5 year review. ksr 05-08-03 Raymond Monnin D Boilerplate update, part of 5 year review. ksr 11-03-08 Charles F. Saffle CURRENT CAGE CODE 67268 THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2

4、 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY S. Rooney DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael A. Frye COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, MEMORY, DIGITAL, CMOS 1

5、6K STATIC RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 17 June 1985 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 84132 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E167-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license

6、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-

7、PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84132 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Dev

8、ice type Generic number 1/ Circuit function Access time 01 85 ns 02 45 ns 03 (16K x 1 SRAM) 70 ns 04 35 ns 05 35ns 06 25 ns 07 25 ns 08 55 ns 09 45 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package

9、style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line package S GDFP2-F20 or CDFP3-F20 20 Flat package Y CQCC3-N20 20 Rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range(VCC) . -0.3 V dc to +7.0

10、 V dc 2/ Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1.0 W Lead temperature (soldering, 5 seconds) . +270C Thermal resistance (JC) . See MIL-STD-1835 Junction temperature (TJ) 3/ . +150C 1.4 Recommended operating conditions. Case operating temperature range . -55C to +12

11、5C Supply voltage range(VCC) 4.5 V dc to 5.5 V dc 1/ 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ All voltages referenced to VSS. 3/ Maximum junction temperature shall not be exceed

12、ed except for allowable short duration burn-in screening conditions as specified in method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990

13、 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents

14、are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component

15、 Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbin

16、s Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

17、 specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer L

18、isting (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML

19、flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with

20、MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as

21、 specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.5 Die overcoat. Polyimide and silicone coatings

22、 are allowable as an overcoat on the die for alpha particle protection, provided that each coated microcircuit inspection lot as specified in MIL-PRF-38535 shall be subjected to and pass the internal moisture content test, (method 1018 of MIL-STD-883); the frequency of the internal water vapor testi

23、ng may not be decreased unless approved by the preparing activity. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test

24、 requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132

25、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ Group A Device Unit -55C VCC- 0.2 V OR 0.2 V 04,06 900 07 10 Supply current ICC4VCC= 2.0 V, IO= 0 A 1,2,3 01,03, 40 A (data

26、 CE = WE = VCC 09,04 200 retention) 06 Low level VOLVCC= 4.5 V; IOL= 8 mA 1,2,3 All 0.4 V output voltage High level VOHVCC= 4.5 V; IOH= -4 mA 1,2,3 All 2.4 V output voltage 01,03 -1.0 1.0 Input leakage IILVIN= GND 1,2,3 02,05 -10 10 A current IIHVIN= 5.5 V 07,09 04,06 -5 5 08 High impedance IOHZVOUT

27、= 5.5 V CE = VCC 01,03 -1.0 1.0 output leakage 1,2,3 current 07 -10 10 A IOLZVOUT= GND CE = VIH 1,2,3 02,05 -20 20 08,09 04,06 -5 5 Low level VIL 1,2,3 All 0.8 V input voltage High level VIH 1,2,3 All 2.2 V input voltage 2/ Input capacitance CINTC= +25C, VCC= GND 4 All 8 pF VIN= GND, f = 1 MHz see 4

28、.3.1c 2/ Output capacitance COUTTC= +25C, VCC= GND 4 All 10 pF VOUT= GND, f = 1 MHz see 4.3.1c See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132 DLA LAND AND MARITIME COLUMBUS, O

29、HIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 3/ 4/ Group A Device Unit -55C TC +125C subgroups type Min Max VSS= 0 V 4.5 V VCC 5.5 V unless otherwise specified Read or write tAVAV See figur

30、e 5 9,10,11 01 85 ns cycle time 02,09 45 03 70 08 55 04,05 35 06,07 25 Address access tAVQV 9,10,11 01 85 ns time 02,09 45 03 70 08 55 04,05 35 06,07 25 Chip enable tELQV 9,10,11 01 85 ns access time 02,09 45 03 70 08 55 04,05 35 06,07 25 Chip enable to tEHQZ 9,10,11 01,03 40 ns output in 2/ 02,08 2

31、5 high Z 05,09 04 15 06,07 10 Output hold tAVQX 9,10,11 01,03, 5 ns after address 2/ 04,06, change 07 02,05 3 08,09 Chip enable to tELQX 9,10,11 01,03, 5 ns output active 2/ 07 02,08, 3 09 Write enable tWLWH 9,10,11 01 45 ns pulse width 03,08 40 during write 02,04 30 05,09 06,07 20 Chip enable to tE

32、LWH 9,10,11 01 65 ns end of write 02,09 35 03 55 04,05 30 08 45 06,07 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISIO

33、N LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 3/ 4/ Group A Device Unit -55C TC +125C subgroups type Min Max VSS= 0 V 4.5 V VCC 5.5 V unless otherwise specified Data setup to tDVWH See figure 5 9,10,11 01 35 ns e

34、nd of write 02,08, 25 09 03 30 04,05 25 06,07 15 Data hold after tWHDX 9,10,11 All 5 ns end of write Address setup tAVWH 9,10,11 01 65 ns to end of 02,09 35 write 03 55 04,05 30 06,07 20 08 45 Write recovery tWHAV 9,10,11 02,05 5 ns time 2/ 08,09 01,03 0 04,06 07 Write-enable tWLQZ 9,10,11 01,03, 40

35、 ns low to output 2/ 02,09, 30 in high Z 08 25 05 20 04 15 06,07 10 Write-enable tWHQZ 9,10,11 All 0 ns high to output 2/ invalid Address setup tAVWL 9,10,11 01,03 0 ns before write 04,06 low 07 02,05 08,09 5 1/ All voltages referenced to VSS. 2/ Tested initially and after any design and or process

36、changes which may affect this parameter. 3/ AC measurements assume transition time 5 ns and input level are from VSSto 3.0 V. See figure 5. Timing transitions are at 1.5 V. 4/ For timing waveforms, see figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 84132 DLA LAND AND MARITI