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本文(DLA SMD-5962-85130 REV D-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL BUFFER WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf)为本站会员(eventdump275)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-85130 REV D-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL BUFFER WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Convert to military drawing format. Add vendor CAGE 01295 for device type 01. Table I, delete output capacitance jt 87-01-08 N. A. Hauck B Update boilerplate to MIL-PRF-38535 requirements. jak 01-11-16 Thomas M. Hess C Add class V criteria. Add c

2、ase outline S. Correct footnotes in sections 1.3 and 1.4. Correct waveforms and notes in figure 4. Add table III, delta limits. Editorial changes throughout. jak 03-08-05 Thanh V. Nguyen D Add JEDEC Standard 7-A in paragraphs 2.2 and 4.4.1c. Update boilerplate paragraphs to the current MIL-PRF-38535

3、 requirements. - LTG 09-11-23 Thomas M. Hess CURRENT CAGE CODE IS 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Greg A. Pitz DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICRO

4、CIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY D. A. DiCenzo APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL BUFFER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVA

5、L DATE 86-03-07 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 85130 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E045-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS

6、, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and

7、 are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 85130 01 R A Drawing number Device type (see 1.2.2) Case outline(

8、see 1.2.4) Lead finish(see 1.2.5)For device class V: 5962 - 85130 01 V R A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) /Drawing number 1.2.1 RHA designator. Device classes Q and

9、V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.

10、2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT244 Octal buffer with three-state outputs, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product

11、assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device. Device class Device requirements documentation M Vendor self-certifi

12、cation to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descr

13、iptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device

14、class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply vol

15、tage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+ 0.5 V dc DC output voltage . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) . 20 mA DC output current (per pin) 35 mA DC VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximu

16、m power dissipation (PD) 500 mW 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (

17、TC) . -55C to +125C Input rise or fall time: VCC= 5.0 V . 0 to 500 ns 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are refer

18、enced to GND. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FOR

19、M 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitatio

20、n or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFE

21、NSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphi

22、a, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 7-A - St

23、andard for Description of 54/74HCXXXXX and 54/74HCTXXXXX High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict betwe

24、en the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements

25、 for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

26、 device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q

27、 and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figu

28、re 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

29、ANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characterist

30、ics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in

31、table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the

32、 device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification

33、 mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-3

34、8535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compl

35、iance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.

36、7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device

37、class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option

38、to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group numbe

39、r 37 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electric

40、al performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VIL, VIH= 2.0 V IOH= -20 A, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 4.4 V VIN= VIHor VIL, VIH= 2.0 V IOH= -6.0 mA, VIL= 0.8 V VC

41、C= 4.5 V 1, 2, 3 3.7 Low-level output voltage VOLVIN= VIHor VIL, VIH= 2.0 V IOL= +20 A, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 0.1 V VIN= VIHor VIL, VIH= 2.0 V IOL= +6.0 mA, VIL= 0.8 V VCC= 4.5 V 1, 2, 3 0.4 High-level input voltage VIH2/ VCC= 4.5 V 1, 2, 3 2.0 V Low-level input voltage VIL2/ VCC= 4.5 V 1, 2

42、, 3 0.8 V Quiescent current ICCVIN= VCCor GND, VCC= 5.5 V 1, 2, 3 160 A Additional quiescent supply current ICCVIN= 2.4 V, any one input VIN= VCCor GND, other inputs VCC= 5.5 V, IOUT= 0 A 1, 2, 3 3.0 mA Input leakage current IINVIN= VCCor GND, VCC= 5.5 V 1, 2, 3 1.0 A Three-state output leakage curr

43、ent IOZVIN(Enable) = VIHall other inputs VIN= VIHor VILVOUT= VCCor GND 1, 2, 3 10.0 A Input capacitance CINVIN= 0.0 V, TC= +25C See 4.4.1c 4 10 pF Output capacitance COUTVOUT= 0.0 V, TC= +25C See 4.4.1c 4 20 pF Functional tests See 4.4.1b 7 Propagation delay time, mAn to mYn tPLH, tPHL3/ CL= 50 pF S

44、ee figure 4 9 28 ns 10, 11 42 Propagation delay time, output enable, mOE to mYn tPZH, tPZL3/ CL= 50 pF See figure 4 9 35 ns 10, 11 53 Propagation delay time, output disable, mOE to mYn tPHZ, tPLZ3/ CL= 50 pF See figure 4 9 35 ns 10, 11 53 Transition time tTHL, tTLH4/ CL= 50 pF See figure 4 9 12 ns 1

45、0, 11 18 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage and so the 5.5 V values should be

46、used. Power dissipation capacitance (CPD), typically 40 pF, determines the no load dynamic power consumption, PD= CPD VCC2f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ Test not required if applied as a forcing function for VOHor VOL. 3/ For propagation delay tests, all

47、paths must be tested. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS C

48、OLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines R, S, and 2 Terminal number Terminal symbol 1 1OE 2 1A13 2Y4 4 1A25 2Y3 6 1A37 2Y2 8 1A49 2Y1 10 GND 11 2A1 12 1Y413 2A2 14 1Y315 2A3 16 1Y217 2A4 18 1Y119 2OE 20 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 85130 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Inputs Ou

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