DLA SMD-5962-86011 REV D-2011 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS DECADE COUNTER DIVIDER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Convert to military drawing format. Add vendor CAGE 27014 for device type 01EX and 012X. 87-01-27 Nelson A. Hauck B Update boilerplate to MIL-PRF-38535 requirements. jak 01-11-26 Thomas M. Hess C Made change to paragraph 3.5. Update boilerplate t

2、o MIL-PRF-38535 requirements. LTG 05-01-26 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-09-26 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMI

3、C N/A PREPARED BY Jeffery Tunstall DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Nelson A. Ha

4、uck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, DECADE COUNTER/DIVIDER, MONOLITHIC SILICON DRAWING APPROVAL DATE 86-01-22 REVISION LEVEL D SIZE A CAGE CODE 14933 86011 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E490-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

5、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PR

6、F-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 86011 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Devic

7、e type Generic number Circuit function 01 54HC4017 Decade counter/divider 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square leadless

8、 chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC+0.5 V dc DC output voltage . -0.5 V dc to VCC+0.5 V dc Clamp diode current. 20 m

9、A DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ)

10、 +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performanc

11、e and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided

12、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time, ena

13、ble to clock (tS): TC= +25C: VCC= 2.0 V 75 ns VCC= 4.5 V 15 ns VCC= 6.0 V 13 ns TC= -55C to 125C: VCC= 2.0 V 110 ns VCC= 4.5 V 22 ns VCC= 6.0 V 19 ns Minimum clock input pulse width (tw1) TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to 125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30

14、ns VCC= 6.0 V 26 ns Minimum hold time, clock to enable (th): TC= +25C: VCC= 2.0 V 75 ns VCC= 4.5 V 15 ns VCC= 6.0 V 13 ns TC= -55C to 125C: VCC= 2.0 V 110 ns VCC= 4.5 V 22 ns VCC= 6.0 V 19 ns Minimum pulse width, reset input (tw2): TC= +25C: VCC= 2.0 V 80 ns VCC= 4.5 V 16 ns VCC= 6.0 V 14 ns TC= -55

15、C to 125C: VCC= 2.0 V 120 ns VCC= 4.5 V 24 ns VCC= 6.0 V 20 ns Minimum enable pulse width (tw3) TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to 125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum recovery time, reset to clock (trec): TC= +25C: VCC= 2.0 V 100 n

16、s VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to 125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVIS

17、ION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Maximum clock frequency (fMAX): TC= +25C: VCC= 2.0 V 4 MHz VCC= 4.5 V 20 MHz VCC= 6.0 V 24 MHz TC= -55C to 125C: VCC= 2.0 V 2.6 MHz VCC= 4.5 V 13 MHz VCC= 6.0 V 15 MHz 2. APPLICABLE DOCUMENTS 2.1 Government s

18、pecification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL

19、-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcir

20、cuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. Th

21、e following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 5

22、4/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of thi

23、s drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accor

24、dance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-3

25、8535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications sh

26、all not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networki

27、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specifi

28、ed in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagr

29、am. The logic diagram shall be as specified on figure 3. 3.2.5 Counting sequence. The counting sequence shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristic

30、s. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

31、 tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). 3.5.1 Certifica

32、tion/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is use

33、d. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of s

34、upply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this

35、drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufactur

36、ers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME

37、 COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1,

38、 2, 3 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -4.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -5.2 mA VCC= 6.0 V 5.2 Low-level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +5.2

39、mA VCC= 6.0 V 0.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V, TC= +25C, See 4.3.1c 4 10 pF Quiescent current ICCVIN= VCCor GND, VCC= 6.0 V

40、1, 2, 3 160 A Input leakage current IINVIN= VCCor GND, VCC= 6.0 V 1, 2, 3 1.0 A Functional tests See 4.3.1d 7 Propagation delay, time, CP to Qn tPLH1, tPHL13/ CL= 50 pF See figure 5 VCC= 2.0 V 9 230 ns 10, 11 345 VCC= 4.5 V 9 4610, 11 69 VCC= 6.0 V 9 3910, 11 59 See footnotes at end of table. Provid

41、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symb

42、ol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay, time, CP to CO tPLH2, tPHL23/ CL= 50 pF See figure 5 VCC= 2.0 V 9 230 ns 10, 11 345 VCC= 4.5 V 9 46 10, 11 69 VCC= 6.0 V 9 39 10, 11 59 Propagation delay, time, CE to CO tPHL3, tPL

43、H33/ CL= 50 pF See figure 5 VCC= 2.0 V 9 250 ns 10, 11 375 VCC= 4.5 V 9 50 10, 11 75 VCC= 6.0 V 9 43 10, 11 64 Propagation delay, time, CE to Qn tPHL4, tPLH43/ CL= 50 pF See figure 5 VCC= 2.0 V 9 250 ns 10, 11 375 VCC= 4.5 V 9 50 10, 11 75 VCC= 6.0 V 9 43 10, 11 64 Propagation delay, time, MR to Qn

44、tPHL5, tPLH53/ CL= 50 pF See figure 5 VCC= 2.0 V 9 230 ns 10, 11 345 VCC= 4.5 V 9 46 10, 11 69 VCC= 6.0 V 9 39 10, 11 59 Propagation delay, time, MR to CO tPLH63/ CL= 50 pF See figure 5 VCC= 2.0 V 9 230 ns 10, 11 345 VCC= 4.5 V 9 46 10, 11 69 VCC= 6.0 V 9 39 10, 11 59 See footnotes at end of table.

45、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86011 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Tes

46、t Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Transition time tTHL, tTLH4/ CL= 50 pF See figure 5 VCC= 2.0 V 9 75 ns 10, 11 110 VCC= 4.5 V 9 1510, 11 22 VCC= 6.0 V 9 1310, 11 19 1/ For a power supply of 5.0 V 10% the worst case output volt

47、age (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher vol

48、tage and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 40 pF, determines the no load dynamic power consumption, PD= CPD VCC2 f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ Test not required if applied as a forcing function for VOHor VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified parameters in table I. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided b