DLA SMD-5962-86062 REV E-2012 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS OCTAL INVERTING D-TYPE LATCH WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE 01295 to case outlines R and 2. Add vendor CAGE 27014 to case outline 2. 87-09-23 M. A. Frye B Change CAGE code to 67268. Add case outline S to drawing. Add vendor CAGE 01295 to case outline S. Remove vendor CAGE 04713 from drawin

2、g. Editorial changes to table I. Editorial changes throughout. 89-07-24 M. A. Frye C Update boilerplate to MIL-PRF-38535 requirements. jak 01-12-04 Thomas M. Hess D Update boilerplate to MIL-PRF-38535 requirements. - LTG 07-11-28 Thomas M. Hess E Correct VOHand VOLtest condition IOin table I. Update

3、 boilerplate to MIL-PRF-38535 requirements. - jak 12-12-14 Thomas M. Hess Current CAGE CODE is 67268 REV SHEET REV SHEET REV STATUS REV E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Greg a. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.

4、landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL INVERTING D-TYPE LATCH WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPART

5、MENT OF DEFENSE DRAWING APPROVAL DATE 86-07-17 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 14933 5962-86062 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E105-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8606

6、2 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number

7、(PIN). The complete PIN is as shown in the following example: 5962-86062 01 R A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54

8、HC563 Octal inverting D-type latch with three-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC

9、1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHI

10、O 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range -0.5 V dc to VCC+0.5 V dc DC output voltage range -0.5 V dc to VCC+0.5 V dc DC input diode current . 20 mA DC output diode current. 20

11、 mA DC output current (per pin) 35 mA DC VCCor GND current (per pin) . 70 mA Maximum power dissipation (PD) . 500 mW 2/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Junction temperature (TJ) . +175C Storage temperature range (TSTG) . -65C

12、 to +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) -55C to +125C Input rise or fall time: VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns Minimum setup time (tS): TC= +25C: VCC= 2.0 V 75 ns VCC

13、= 4.5 V 15 ns VCC= 6.0 V 13 ns TC= -55C/+125C: VCC= 2.0 V 110 ns VCC= 4.5 V 22 ns VCC= 6.0 V 19 ns Minimum hold time (th): TC= +25C: VCC= 2.0 V 50 ns VCC= 4.5 V 10 ns VCC= 6.0 V 9 ns TC= -55C/+125C: VCC= 2.0 V 75 ns VCC= 4.5 V 15 ns VCC= 6.0 V 13 ns Minimum pulse width (tW): TC= +25C: VCC= 2.0 V 80

14、ns VCC= 4.5 V 16 ns VCC= 6.0 V 14 ns TC= -55C/+125C: VCC= 2.0 V 120 ns VCC= 4.5 V 24 ns VCC= 6.0 V 20 ns 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted w

15、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handb

16、ooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF

17、 DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents

18、are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

19、 this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class

20、 level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance wit

21、h the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. T

22、hese modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be

23、as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 L

24、ogic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

25、IRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over t

26、he full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The

27、part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certificati

28、on/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used.

29、 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supp

30、ly shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this dra

31、wing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturer

32、s facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARIT

33、IME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max High-level output voltage VOHVIN= VIHor VILIO 20 A VCC= 2.0 V 1,

34、 2, 3 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIO 6.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIO 7.8 mA VCC= 6.0 V 5.2 Low-level output voltage VOLVIN= VIHor VILIO 20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIO 6.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIO 7.8 mA VCC= 6.0 V 0

35、.4 High-level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low-level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent current ICCVIN= VCCor GND VCC= 6.0 V 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND VCC= 6.0 V 1, 2, 3 1.0 A

36、 Three-state output leakage current IOZVOUT= VCCor GND VIN= VIHor VIL1, 2, 3 10.0 A Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Output capacitance COUTVIN= 0.0 V, TC= +25C See 4.3.1c 4 20 pF Functional tests See 4.3.1d 7 Propagation delay time, Dn to On tPLH1, tPHL13/ CL= 50 pF See

37、figure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 30 10, 11 45 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS,

38、 OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Propagation delay time, LE to On tPLH2, tPHL23/ CL= 50 pF See fig

39、ure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 30 10, 11 45 Propagation delay time, output enable, OE to On tPZH, tPZL3/ CL= 50 pF See figure 4 VCC= 2.0 V 9 175 ns 10, 11 265 VCC= 4.5 V 9 35 10, 11 53 VCC= 6.0 V 9 30 10, 11 45 Propagation delay time, output disable, OE t

40、o On tPHZ, tPLZ3/ CL= 50 pF See figure 4 VCC= 2.0 V 9 150 ns 10, 11 225 VCC= 4.5 V 9 30 10, 11 45 VCC= 6.0 V 9 26 10, 11 38 Transition time, output rise and fall tTHL, tTLH4/ CL= 50 pF See figure 4 VCC= 2.0 V 9 60 ns 10, 11 90 VCC= 4.5 V 9 12 10, 11 18 VCC= 6.0 V 9 10 10, 11 15 1/ For a power supply

41、 of 5.0 V 10% the worst case output voltage (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VINand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at VCC= 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, a

42、nd IOZ) occur for CMOS at the higher voltage so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 50 pF, determines the no load dynamic power consumption, PD= CPD VCC2 f+ICC VCC; and the no load dynamic current consumption, IS= CPDVCCf+ICC. 2/ VIHand VILtests not requir

43、ed if applied as forcing functions for VOHor VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the limits specified in table I. 4/ Transition times (tTLH, tTHL) shall be guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleN

44、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines R, S and 2 Terminal number Terminal symbol 1 OE 2 D03 D14 D2

45、5 D36 D47 D58 D69 D710 GND 11 LE 12 O713 O614 O515 O416 O317 O218 O119 O020 VCCPin Description Symbol Description Dn (n = 0 to 7) Data inputs On (n = 0 to 7) Data outputs LE Latch enable control input (active low) OE Output enable control input (active low) FIGURE 1. Terminal connections. Provided b

46、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 9 DSCC FORM 2234 APR 97 Inputs Outputs OE LE Dn On L H H L L H L H L L l H L L h L H X X Z H

47、= High voltage level L = Low voltage level X = Irrelevant Z = High impedance l = Low voltage level one set-up time prior to the high to low latch enable transition h = High voltage level one set-up time prior to the high to low latch enable transition FIGURE 2. Truth table. FIGURE 3. Logic diagram.

48、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86062 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 10 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-