DLA SMD-5962-86063 REV H-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 262 144-BIT (32K X 8) UV ERASABLE PROM MONOLITHIC SILICON《硅单块 144比特(32KX8)紫外可擦拭程序262互补金属氧化物半导体 数字主存储器微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add three vendors, 18324, 1FN41, and 66579. Add device types 04, 05, 06, and 07. Add margin test method C. Update vendors PIN. Change code indent. no. to 67268. Editorial changes throughout. 87-12-17 M. A. Frye B Add device type 08 with vendors C

2、AGE 1FN41 and CAGE 66579. Added time temperature regression equation for unbiased bake. Removed vendor CAGE 66302. Made technical changes to table I, 4.2 back end margin test method step 3, 4.3.1 step C, table II, and table III. Editorial changes throughout. Added vendors PIN from XMB/883 to either

3、LM/883 for appropriate device types. Deleted the top CE waveform on figure 6. This was incorrect for this device. 89-01-01 M. A. Frye C Added vendor CAGE 34335 to the drawing as a source of supply for device types 01 through 07. Add vendor CAGE number 66579 to device types 01 through 04, also add ve

4、ndor CAGE number 01295 to devices 04XX and 05XX. Add test condition A to 4.2 and 4.3.2. Add margin test method E for vendor CAGE number 34335. Change to vendor similar PIN for vendor CAGE numbers 1FN41 and 66579. Change to figure 3, margin test method C for vendor CAGE 01295 and change to programmin

5、g waveforms. Change to 4.5. Editorial changes throughout. Add case outline Z for vendor CAGE number 1FN41. 90-12-05 M. A. Frye D Changes in accordance with NOR 5962-R130-92. 92-01-30 M. A. Frye E Add case outline U. Add device types 09 and 10. Remove vendor 27014 from drawing. Editorial changes thro

6、ughout. 93-10-15 M. A. Frye F Changes in accordance with NOR 5962-R118-94. 94-02-16 M. A. Frye G Updated boilerplate. Added device types 11-21. Removed vendors 1FN41, 18324, 34335, and 61394 from drawing. Added vendor 65786 to drawing. Removed margin test methods from drawing. 97-06-11 Raymond Monni

7、n H Boilerplate update, part of 5 year review. ksr 06-07-17 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE IS 67268 REV SHET REV H H SHET 15 16 REV STATUS REV H H H H H H H H H H H H H H OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED B

8、Y James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Michael A. Frye DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE

9、 87-02-12 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 262,144-BIT (32K x 8) UV ERASABLE PROM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL H SIZE A CAGE CODE 14933 5962-86063 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E528-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license

10、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86063 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) a

11、nd space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following ex

12、ample: For device class M: 5962 - 86063 01 X X Federal RHA Device Case Lead stock class designator type outline finish designator (see 1.2.1) (see 1.2.2) (see 1.2.4) (see 1.2.5) / / Drawing number For device classes Q and V: 5962 - 86063 01 Q X X Federal RHA Device Device Case Lead stock class desig

13、nator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device

14、class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit Access t

15、ime 01,11 (see 6.6) 32K x 8-bit UV EPROM 200 ns 02,12 (see 6.6) 32K x 8-bit UV EPROM 250 ns 03,13 (see 6.6) 32K x 8-bit UV EPROM 300 ns 04,14 (see 6.6) 32K x 8-bit UV EPROM 170 ns 05,15 (see 6.6) 32K x 8-bit UV EPROM 150 ns 06,16 (see 6.6) 32K x 8-bit UV EPROM 120 ns 07,17 (see 6.6) 32K x 8-bit UV E

16、PROM 90 ns 08,18 (see 6.6) 32K x 8-bit UV EPROM 70 ns 09,19 (see 6.6) 32K x 8-bit UV EPROM 55 ns 10,20 (see 6.6) 32K x 8-bit UV EPROM 45 ns 21 (see 6.6) 32K x 8-bit UV EPROM 35 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as

17、 follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 Provided by IHSNot for ResaleNo

18、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86063 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and

19、as follows: Outline letter Descriptive designator Terminals Package style 1/ X GDIP1-T28 or CDIP2-T28 28 Dual-in-line Y CQCC1-N32 32 Rectangular leadless chip carrier Z See figure 1 32 J-lead chip carrier U CDIP3-T28 or GDIP4-T28 28 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in

20、MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. Storage temperature - -65C to +150C Input voltages with respect to ground - +6.5 V dc to -0.3 V dc Output voltages with respect to ground - VCC+0.3 V dc to GND -0.3 V dc VPPsupply

21、voltage with respect to ground - +14.0 V dc to -0.6 V dc Power dissipation (PD) 2/ - +500 mW Lead temperature (soldering, 10 seconds)- +300C Thermal resistance, junction-to-case (JC): Case outlines X, Y, and U - See MIL-STD-1835 Case outline Z - 13C/W Junction temperature (TJ) - +150C 1.4 Recommende

22、d operating conditions. Case operating temperature (TC) - -55C to +125C Supply voltage (VCC)- +4.5 V dc to +5.5 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifi

23、ed herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard

24、Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quic

25、ksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes p

26、recedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo

27、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86063 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for devic

28、e classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device cl

29、ass M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or

30、MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table shall be as specifi

31、ed on figure 3. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices shall be as specified on figure 3. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to tes

32、t. A minimum of 50 percent of the total number of cells shall be programmed. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not a part of this drawing. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herei

33、n, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electri

34、cal tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has t

35、he option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certi

36、fication/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Processing EPROMS. All testing requirements and quality assurance prov

37、isions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.5. 3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specifi

38、ed pattern using the procedures and characteristics specified in 4.6. 3.6.3 Verification of state of EPROMS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to ver

39、ify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and shall be removed from the lot. 3.7 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manu

40、facturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted

41、to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. Provided by IHSNot

42、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86063 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Conditions Limits T

43、est Symbol -55C TC +125C Device Group A Unit 4.5 V dc VCC 5.5 V dc type subgroups Min Max unless otherwise specified Input load current ILIVIN= 0 to 5.5 V All 1, 2, 3 +10 A Output leakage ILO1/ VOUT= 0 to 5.5 V All 1, 2, 3 +10 A current 2/ 3/ 11-20 60 Operating current ICC1CE = OE = VIL01-05 1, 2, 3

44、 50 mA TTL inputs VPP= VCC 06 65 00-7= 0 mA 07 70 1 08 90 f = tACCmaximum 09 115 10 130 21 85 Operating current ICC2 01,02, 1, 2, 3 25 mA CMOS inputs 03 04,05 40 06 55 07,11-20 60 08,09 90 10 100 21 85 Standby current ISB1CE = VIH01-05 1, 2, 3 3 mA TTL inputs VCC= 5.5 V, f = 0 MHz 06,07, 5 08,09, 10 45 11-21 25 Standby current ISB2 01-07, 1, 2, 3 300 A CMOS inputs 08,09, 10 45 mA 11-21 25 VPPread current IPPVPP= VCC= 5.5 V 01-10 1,