DLA SMD-5962-86081 REV C-2010 MICROCIRCUIT MEMORY DIGITAL NMOS 16K (4096 X 4- BIT) STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device types 05 and 06. Change parameter tOWfor device types 03 and 04. Add a 20 terminal LCC package. 87-04-29 N. A. Hauck B Changes in accordance with NOR 5962-R155-96. ksr 96-06-26 Michael A. Frye C Update drawing to current requirements.

2、Editorial changes throughout. ksr. 10-02-19 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED CURRENT CAGE CODE 67268 REV SHET REV C SHET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DEFENS

3、E SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Robert P. Evans MICROCIRCUIT, MEMORY, DIGITAL, NMOS 16K (4096 X 4- BIT) STATIC RANDOM ACCESS MEMORY (SRAM)

4、, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-06-27 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 14933 5962-86081 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E108-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

5、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MI

6、L-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86081 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follo

7、ws: Device type Generic number Circuit organization Address access time 01 2168-55 4096X 4 SRAM 55 ns 02 2168-70 4096X 4 SRAM 70 ns 03 2169-50 4096X 4 SRAM 50 ns 04 2169-70 4096X 4 SRAM 70 ns 05 2168-45 4096X 4 SRAM 45 ns 06 2169-40 4096X 4 SRAM 40 ns 1.2.2 Case outline(s). The case outline(s) are a

8、s designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 OR CDIP2-T20 20 dual-in-line package X See figure 1 20 rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute

9、 maximum ratings. VCCsupply voltage range . -0.5 V dc to +7.0 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) . 1.2 W Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC): Case R See MIL-STD-1835 Case X 15 C/W Junction temperature (TJ)

10、+175C DC output current . 20 mA All signal voltages with respect to GND . -3.5 V dc to +7.0 V dc 1.4 Recommended operating conditions. VCCsupply voltage range . 4.5 V dc minimum to 5.5 V dc maximum Minimum hgih-level input voltage (VIH) 2.2 V dc Maximum low-level input voltage (VIL) . 0.8 V dc Case

11、operating temperature range (TC) . -55C to +125C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2

12、. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

13、DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS M

14、IL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-509

15、4.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIRE

16、MENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer

17、 or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM)

18、 plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QM

19、L flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Logic diagram

20、. The logic diagram shall be as specified on figure 2. 3.2.3 Terminal connections. The terminal connections shall be as specified on figure 3. 3.2.4 Truth table. The truth table shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the elec

21、trical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in tabl

22、e I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the ma

23、nufacturer has the option of not marking the “5962-“ on the device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC

24、 FORM 2234 APR 97 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identif

25、y when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an appro

26、ved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits del

27、ivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required

28、documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004

29、 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisi

30、on level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interi

31、m and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 o

32、f MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CINand COUTmeasurement)

33、shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output t

34、erminals tested. d. Subgroups 7, 8A, and 8B shall consist of verifying the truth table specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHI

35、O 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ 2/ Group A subgroups Device type Limits Unit Min Max Output high current IOHVOH= 2.4 V; VCC= 4.5 V 1, 2, 3 All -4 mA Output low current IOLVOL= 0.4 V;

36、VCC= 4.5 V 1, 2, 3 All 8 mA Input high voltage VIH1, 2, 3 All 2.2 6.0 V Input low voltage VIL3/ 1, 2, 3 All -0.5 0.8 V Input load current IIXGND VI VCC1, 2, 3 All -10 10 A Output leakage current IOZGND VO VCCOutput disabled 1, 2, 3 All -50 50 A VCCoperating supply current ICCMaximum VCC, CE VILOutpu

37、t open 1, 2, 3 All 160 mA Automatic CE power down current ISBMaximum VCC, CE VIH1, 2, 3 01,02,05 30 mA 03,04,06 N/A Output short-circuit current IOS4/ 1, 2, 3 All -400 400 mA Input capacitance CI 4/ Test frequency = 1.0 MHz TA= +25C, All pins at 0 V, VCC= 5 V 4 All 5 pF Input/output capacitance CI/O

38、4/ 4 All 7 pFAddress valid to address do not care time (read cycle time) tRCSee figures 5 and 6 9,10,11 01,03 50 ns 02,04 70 05,06 40 Address valid to data out valid delay (address access time) tAA9,10,11 01,03 50 ns 02,04 70 05,06 40 Chip enable low to data valid (chip enable access time) tACS9,10,

39、11 01 55 ns 02 70 03 25 04 30 05 45 06 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6

40、 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 2/ Group A subgroups Device type Limits Unit Min Max Chip enable low CE to data out on tLZ4/ 5/ See figures 5 and 7 9,10,11 01,02,05 5 ns 03,04,06 2 Chip enable high to data ou

41、t off tHZ4/ 5/ 9,10,11 01,03 0 25 ns 02,04 0 30 05,06 0 20 Address unknown to data out unknown time tOH4/ See figures 5 and 6 9,10,11 All 1 ns Chip enable high to power down delay tPD4/ 9,10,11 01 55 ns 02 70 05 45 Chip enable low CE to power up delay tPU4/ 9,10,11 01,02,05 0 ns Address valid to add

42、ress do not care (write cycle time) tWC9,10,11 01,03 50 ns 02,04 70 05,06 40 Write enable low to write enable high tWP6/ 9,10,11 01,03 45 ns 02,04 65 05,06 35 Write enable high to address do not care tWR9,10,11 All 0 ns Write enable low to output in high Z tWZ4/ 5/ See figures 5 and 7 9,10,11 01,03

43、0 20 ns 02,04 0 25 05,06 0 15 Data in valid to write enable high tDWSee figures 5 and 6 9,10,11 01,03 25 ns 02,04 35 05,06 20 Data hold time tDH9,10,11 All 5 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

44、ICROCIRCUIT DRAWING SIZE A 5962-86081 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 1/ 2/ Group A subgroups Device type Limits Unit Min Max Addr

45、ess valid to write enable low tASSee figures 5 and 6 9,10,11 All 0 ns Chip enable low to write enable high tCW6/ 9,10,11 01,03 50 ns 02,04 70 05,06 40 Write enable high to output in low Z tOW4/ 5/ See figures 5 and 7 9,10,11 01,02,05 5 ns 03,04,06 0 Address valid to end of write tAWSee figures 5 and

46、 6 9,10,11 01,03 50 ns 02,04 70 05,06 40 1/ Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified IOL/ IOHand 30 pF load capacitance. Output timing reference is 1.5 V 2/ The operating cas

47、e temperature range is guaranteed with transverse air flow of 400 linear feet per minute. 3/ VILvoltage of less than -0.5 V on the I/O pins will cause the output current to exceed the maximum rating and thus should not exceed 30 seconds in duration. 4/ Tested initially and after any design or proces

48、s changes which may affect this parameter. 5/ Transition is measured at 1.5 V on the input to VOH-500 mV and VOL+500 mV on the outputs using the load shown on figure 7. CL= 5 pF. 6/ The internal write time of the memory is defined by the overlap of CE low and WE low. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Provided by IHSNot for