DLA SMD-5962-86705 REV G-2010 MICROCIRCUIT MEMORY DIGITAL CMOS 4K x 4 STATIC RAM MONOLITHIC SILICON.pdf-资源下载-麦多课文库

DLA SMD-5962-86705 REV G-2010 MICROCIRCUIT MEMORY DIGITAL CMOS 4K x 4 STATIC RAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change CAGE to 67268. Added case outline Z. Added vendor CAGE 60911 and five new device types to drawing. Dropped vendor CAGE 34335 as source of supply. Deleted VCCfor data retention from recommended operating conditions, and added it to table I

2、as ICC4. Moved standard power devices for vendor CAGE number 61772 and 34649 to devices 11-15. Editorial changes throughout. Changes to table I, and correction in vendor similar part number for vendor 04713. Deleted subgroups 1,2,3 from table II. 88-03-04 M. A. Frye B Changes in accordance with NOR

3、5962-R002-91. 91-09-20 M. A. Frye C Changes in accordance with NOR 5962-R104-92. 91-12-24 M. A. Frye D Changes in accordance with NOR 5962-R153-92. 92-02-28 M. A. Frye E Updated boilerplate. Separated source bulletin from body of drawing. -glg 00-07-08 Raymond Monnin F Corrected Table I Conditions b

4、lock for AC parameters from See figures 5 8 to See figure 5 as applicable. Updated boilerplate as part of 5 year review. ksr 06-01-30 Raymond Monnin G Added device types 16 - 25 to drawing. - glg 10-03-09 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 672

5、68 REV SHEET REV SHEET REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWI

6、NG IS AVAILABLE FOR USE BY ALL APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4K x 4 STATIC RAM, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-02-05 AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 14933 5962-86705 SHEET 1 OF 14 DSCC FO

7、RM 2233 APR 97 5962-E055-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. Th

8、is drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962- 86705 01 R A | | | | | | | | | | | | Drawing

9、number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01,11, 16 1/ 4096 x 4 CMOS static RAM 25 ns 02, 17 1/ 4096 x 4 CMOS static

10、RAM 25 ns 03,12, 18 1/ 4096 x 4 CMOS static RAM 35 ns 04, 19 1/ 4096 x 4 CMOS static RAM 35 ns 05,13, 20 1/ 4096 x 4 CMOS static RAM 45 ns 06, 21 1/ 4096 x 4 CMOS static RAM 45 ns 07,14, 22 1/ 4096 x 4 CMOS static RAM 55 ns 08, 23 1/ 4096 x 4 CMOS static RAM 55 ns 09,15, 24 1/ 4096 x 4 CMOS static R

11、AM 70 ns 10, 25 1/ 4096 x 4 CMOS static RAM 70 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line package X CQCC3-N20 20 chip carrier package Y Se

12、e figure 1 20 flat package Z CDFP4-F20 20 flat package U CQCC4-N20 20 chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range -0.5 V dc to VCC+0.5 V dc Storage

13、temperature range . -65C to +150C Maximum power dissipation (PD): 2/ 1.0 W Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) cases R,X,Z,U See MIL-STD-1835 Case Y . 3.8C/W Junction Temperature (TJ) +175C DC output current for device types 01-15 25 mA DC outpu

14、t current for device types 16-25 50 mA 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

15、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-86705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Case operating temperature range (TC) -55C to +125C Maximum low level input low voltage (VIL) . 0.8 V dc Minimum

16、 high level input high voltage (VIH) . 2.4 V dc Supply voltage range (VCC) . 4.5 V dc to 5.5 V dc VCC for data retention (VDR) . 2.2 V dc minimum 2/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of th

17、is drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL

18、-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online a

19、t https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing tak

20、es precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices a

21、nd as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturer

22、s approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications

23、 shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MI

24、L-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth table. The truth table shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with figure 1 and 1.2.2 herein. 3.3 Electric

25、al performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifie

26、d in table II. The electrical tests for each subgroup are described in table I. 2/ Applies to device types 02, 04, 06, 08, and 10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86705 DEFENSE SUPPLY CENTER C

28、 V or | | | | | | | +0.2 V VIN -0.2 V | | | | | Data retention current |ICC4| | VCC= 2.0 V | 1, 2, 3 |02,04,06, | |1200 | A | | | | |08,10,17, | | | | | | | |19,21,23, | | | | | | | | 25 | | | | | | | 01,02,11 | 25 | | | | | | 16,17 | | | Read cycle time |tRC|See figure 5 as applicable | 9, 10, 11 |

29、 03,04,12 | 35 | | ns | | | | 18,19 | | | | | | | 05,06,13 | 45 | | | | | | 20,21 | | | | | | | 07,08,14 | 55 | | | | | | 22,23 | | | | | | | 09,10,15 | 70 | | | | | | 24,25 | | | See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

31、55C TC +125C |subgroups | type | |Unit | | 4.5 V VCC 5.5 V | | | Min | Max | | | unless otherwise specified | | | | | | | | | 01,02,11 | | 25 | | | See figure 5 as applicable | | 16,17 | | | | | | | 03,04,12 | | 35 | Address access time |tAA| | 9, 10, 11 | 18,19 | | | ns | | | | 05,06,13 | | 45 | |

32、| | | 20,21 | | | | | | | 07,08,14 | | 55 | | | | | 22,23 | | | | | | | 09,10,15 | | 70 | | | | | 24,25 | | | | | | | 01,02,11 | | 25 | | | | | 16,17 | | | | | | | 03,04,12 | | 35 | Chip enable access time | tACS | | 9, 10, 11 | 18,19 | | | ns | | | | 05,06,13 | | 45 | | | | | 20,21 | | | | | | | 07

33、,08,14 | | 55 | | | | | 22,23 | | | | | | | 09,10,15 | | 70 | | | | | 24,25 | | | Chip enable low to data |tLZ| | 9, 10, 11 | All | 5 | | ns out on 4/ 5/ | | | | | | | | | | | 01,02,11 | 0 | 10 | | | | | 16,17 | | | | | | | 03,04 | 0 | 15 | Chip enable high to data |tHZ| | 9, 10, 11 | 18,19 | | | ns

34、 out off 4/ 5/ 6/ | | | | 05,06,12 | 0 | 20 | | | | | 13,20,21 | | | | | | | 07,08,14 | 0 | 25 | | | | | 22,23 | | | | | | | 09,10,15 | 0 | 30 | | | | | 24,25 | | | Address unknown to data |tOH| | 9, 10, 11 | All | 3 | | ns out unknown time | | | | | | | | | | | 01,02,11 | | 25 | | | | | 16,17 | | |

35、 | | | | 03,04,12 | | 35 | Chip enable high to | tPD | | 9, 10, 11 | 18,19 | | | ns power down delay 4/ | | | | 05,06,13 | | 45 | | | | | 20,21 | | | | | | | 07,08,14 | | 55 | | | | | 22,23 | | | | | | | 09,10,15 | | 70 | | | | | 24,25 | | | Chip enable low to |tPU| | 9, 10, 11 | All | 0 | | ns powe

36、r on delay 4/ | | | | | | | See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 223

38、figure 5 as applicable | | 16,17 | | | | | | | 03,04,12 | 35 | | Write cycle time | tWC | | 9, 10, 11 | 18,19 | | | ns | | | | 05,06,13 | 45 | | | | | | 20,21 | | | | | | | 07,08,14 | 55 | | | | | | 22,23 | | | | | | | 09,10,15 | 70 | | | | | | 24,25 | | | | | | |01,02,11, | 20 | | | | | | 16,17 | |

39、 | Write enable low to write |tWP| | 9, 10, 11 |03,04,05, | 30 | | ns enable high 7/ | | | |06,12,13, | | | | | | |18-21 | | | | | | |07,08,14, | 45 | | | | | | 22,23 | | | | | | |09,10,15 | 65 | | | | | | 24,25 | | | Write enable high to |tWR| | | 01-10, | 0 | | ns address dont care | | | 9, 10, 11

40、 | 16-25 | | | | | | | 11-15 | 5 | | | | | | 01,02 | 0 | 7 | | | | | 16,17 | | | Write enable low to |tWZ| | 9, 10, 11 |03,11,12, | 0 | 15 | ns output in high Z 4/ 5/ 6/ | | | | 18 | | | | | | | 04,19 | 0 | 13 | | | | |05,06,13, | 0 | 20 | | | | | 20,21 | | | | | | |07,08,14, | 0 | 25 | | | | | 22,2

41、3 | | | | | | |09,10,15, | 0 | 30 | | | | | 24,25 | | | | | | |01,02,11, | 13 | | | | | | 16,17 | | | Valid data in to write |tDW| | 9, 10, 11 | 04,19 | 17 | | ns enable high | | | |03,05,06, | 15 | | | | | |12,13,18, | | | | | | | 20,21 | | | | | | |07,08,14 | 25 | | | | | | 22,23 | | | | | | |09,1

42、0,15, | 30 | | | | | | 24,25 | | | Data hold time |tDH| | 9, 10, 11 | All | 3 | | ns | | | | | | | Address valid to write |tAS| | 9, 10, 11 | All | 0 | | ns enable low | | | | | | | See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

44、 -55C TC +125C |subgroups | type | |Unit | | 4.5 V VCC 5.5 V | | | Min | Max| | | unless otherwise specified | | | | | | | | |01,02,11,16,17 | 20 | | Chip enable low to write |tCW| See figure 5 as applicable | 9, 10, 11 |03,04,12,18,19 | 30 | | ns enable high 4/ 7/ | | | |05,06,13,20,21 | 35 | | | |

45、 | |07,08,14,22,23 | 45 | | | | | |09,10,15,24,25 | 60 | | Write enable high to |tOW| | 9, 10, 11 | All | 0 | | ns output in low Z 4/ 5/ | | | | | | | | | | |01,02,11,16,17 | 20 | | Address valid to end of |tAW| | 9, 10, 11 |03,04,12,18,19 | 30 | | ns write | | | |05,06,13,20,21 | 35 | | | | | |07,0

46、8,14,22,23 | 40 | | | | | |09,10,15,24,25 | 60 | | 1/ Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specific IOL/IOHand 30 pF load capacitance. Output timing reference is 1.5 V. 2/ For tes

47、t and correlation purposes, ambient temperature is defined as the instant on case temperature. 3/ VILvoltages of less than 0.5 V on the I/O pins will cause the output current to exceed the maximum rating. 1.0 V and 3.0 V pulses can be tolerated for up to 50 ns and 10 ns respectively. 4/ This parameter is not tested but is guar

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