DLA SMD-5962-86809 REV D-2009 MICROCIRCUIT DIGITAL NMOS 16-BIT MICROCONTROLLER WITH 8K BYTES OF EPROM MEMORY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R024-92. 91-11-14 Monica L. Poelking B Update SMD boilerplate to MIL-PRF-38535 requirements. Add “QD” device criteria. - CFS 03-10-29 Thomas M. Hess C Correct the tXHQXlimit in table I. - CFS 04-03-01 Thomas M.

2、 Hess D Update boilerplate to current MIL-PRF-38535 requirements. - CFS 09-05-05 Thomas M. Hess REV SHET REV D D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY To

3、dd D. Creek DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, NMOS, 16-BIT AND AGENCIES OF THE DEPARTMENT OF DE

4、FENSE DRAWING APPROVAL DATE 89-08-01 MICROCONTROLLER WITH 8K BYTES OF EPROM MEMORY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-86809 SHEET 1 OF 28 DSCC FORM 2233 APR 97 5962-E289-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

5、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordanc

6、e with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86809 01 Z A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identify the circuit function as fo

7、llows: Device type Generic number Circuit function Frequency 01 8797BH 16-Bit microcontroller with 8k bytes 12 MHz of EPROM memory 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Y See figure 1. 1/

8、 68 Leaded chip carrier with unformed leads Z CMGA3-P68 1/ 68 Grid array style 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Storage temperature range -65C to +150C Voltage on any pin with respect to VSSor ANGND. -0.3 V to +7.0 V Volta

9、ge from EA or VPPto VSSor ANGND -0.3 V to +13.0 V Maximum power dissipation (PD) 1.5 W Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC): Case Y 9.0C/W 2/ Case Z See MIL-STD-1835 Maximum junction temperature (TJ) . +175C 1.4 Recommended operating conditions. C

10、ase operating temperature range (TC) 3/ -55C to +125C Digital supply voltage range (VCC) +4.5 V dc to +5.5 V dc Analog supply voltage range (VREF) +4.5 V dc to +5.5 V dc Power down supply voltage range (VPD). +4.5 V dc to +5.5 V dc Oscillator frequency range (FOSC). 6.0 MHz to 12.0 MHz _ 1/ Lid shal

11、l be transparent to permit ultraviolet light erasure. 2/ When a thermal resistance value is included in MIL-STD-1835, it shall supersede the value herein. 3/ case temperatures are instant on. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

12、ICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this draw

13、ing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-88

14、3 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:

15、/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes prece

16、dence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as s

17、pecified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers appro

18、ved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall

19、not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-

20、PRF-38535 or other alternative approved by the qualifying activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1

21、.2.2 herein and as specified on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Instruction set summary. The instruction set summary shall be as spe

22、cified on figure 4. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.2.6 Programming waveforms. The programming waveforms shall be as specified on figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted w

23、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristic

24、s are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall b

25、e in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not

26、marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF

27、-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q” or “QML” certification mark. 3.6 Certificate of compliance. A certificate of

28、compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets

29、 the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of ch

30、ange to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore

31、at the option of the reviewer. 3.10 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics sp

32、ecified in 4.4. 3.10.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 and table III. 3.10.3 Verification of erasure of programmability of EPROMS. When specified, devices shall be verified as ei

33、ther programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed fr

34、om the lot. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance charac

35、teristics. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC+125C VCC= VPD= 5.0 V 10% VSS= ANGND = 0.0 V fOSC= 6.0 MHz to 12.0 MHz unless otherwise specified Min Max Supply current ICCAll outputs disconnected. 2/ 1, 2, 3 All 275 mA VPDsupply current IPDNormal operation and

36、power-down. 2/ 1, 2, 3 All 1.0 mA VREFsupply current IREF2/ 1, 2, 3 All 8.0 mA Input low voltage (except RESET) VIL2/ 1, 2, 3 All -0.3 0.8 V Input low voltage (RESET) VIL12/ 1, 2, 3 All -0.3 0.7 V Input high voltage (except RESET, NMI, and XTAL1) VIH2/ 1, 2, 3 All 2.0 VCC+ 0.5 V Input high voltage (

37、RESET rising) VIH12/ 1, 2, 3 All 2.4 VCC+ 0.5 V Input high voltage (RESET falling hysteresis) VIH22/ 1, 2, 3 All 2.1 VCC+ 0.5 V Input high voltage (NMI, XTAL1) VIH32/ 1, 2, 3 All 2.2 VCC+ 0.5 V Input leakage current to each pin of HSI Port 3, Port 4, and P2.1 ILIVIN= 0 V to VCC2/ 1, 2, 3 All 10.0 A

38、DC Input leakage current to each pin of Port 0 ILI1VIN= 0 V to VCC2/ 1, 2, 3 All 3.0 A Input high current to EA IIHVIH= 2.4 V 2/ 1, 2, 3 All 100 A Input low current to Port 1, P2.6, and P2.7 IILVIL= 0.45 V 2/ 1, 2, 3 All -125 A Input low current to RESET IIL1VIL= 0.45 V 2/ 1, 2, 3 All -0.25 -2.0 mA

39、Input low current, P2.2, P2.3, P2.4, READY, BUSWIDTH IIL2VIL= 0.45 V 2/ 1, 2, 3 All -50.0 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS

40、COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC+125C VCC= VPD= 5.0 V 10% VSS= ANGND = 0.0 V fOSC= 6.0 MHz to 12.0 MHz unless otherwise spe

41、cified Min Max Output low voltage on Quasi-Bidirectional port pins and Port 3, and Port 4 when used as ports VOLIOL= 0.8 mA 2/ 3/ 1, 2, 3 All 0.45 V Output low voltage on Quasi-Bidirectional port pins and Port 3, and Port 4 when used as ports VOL1IOL= 2.0 mA 2/ 3/ 4/ 5/ 1, 2, 3 All 0.75 V Output low

42、 voltage on standard output pins, RESET, and Bus/Control pins VOL2IOL= 2.0 mA 2/ 3/ 4/ 5/ 6/ 1, 2, 3 All 0.45 V Output high voltage on Quasi-Bidirectional pins VOHIOH= -20 A 2/ 3/ 1, 2, 3 All 2.4 V Output high voltage on standard output pins and Bus/Control pins VOH1IOH= -200 A 2/ 3/ 1, 2, 3 All 2.4

43、 V Output high current on RESET IOH3VOH= 2.4 V 2/ 1, 2, 3 All -50.0 A Pin capacitance CSf = 1.0 MHz See 4.3.1c 2/ 4 All 10 pF Functional tests See 4.3.1e 2/ 7, 8 All READY hold after CLKOUT edge tCLYX9, 10, 11 All 0.0 ns End of ALE/ADV to READY valid tLLYV9, 10, 11 All 2tOSC- 70 ns End of ALE/ADV to

44、 READY high tLLYH9, 10, 11 All 2tOSC+ 40 4tOSC- 70 ns Non-Ready time tYLYH9, 10, 11 All 1000 ns Address valid to input data valid 7/ tAVDVTiming requirements. (System components must meet these specifications.) See figure 5. fOSC= 10.0 MHz 9, 10, 11 All 5tOSC- 120 ns See footnotes at end of table. P

45、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86809 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - C

46、ontinued. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC+125C VCC= VPD= 5.0 V 10% VSS= ANGND = 0.0 V fOSC= 6.0 MHz to 12.0 MHz unless otherwise specified Min Max RD active to input data valid tRLDV9, 10, 11 All 3tOSC 100 ns Data hold after RD inactive tRHDX9, 10, 11 All

47、0.0 ns RD inactive to input data float tRHDZ9, 10, 11 All 0.0 tOSC 25 ns Address valid to BUSWIDTH valid 7/ tAVGV9, 10, 11 All 2tOSC 125 ns BUSWIDTH hold after ALE/ADV low tLLGX9, 10, 11 All tOSC+ 40 ns ALE/ADV low to BUSWIDTH valid tLLGVTiming requirements. (System components must meet these specif

48、ications.) See figure 5. fOSC= 10.0 MHz 9, 10, 11 All tOSC 75 ns Oscillator frequency fOSC9, 10, 11 All 6.0 12.0 MHz Oscillator period tOSCSee figure 5. 9, 10, 11 All 83.0 166 ns XTAL1 rising edge to clockout rising edge tOHCH9, 10, 11 All 0.0 120 ns CLKOUT period 8/ tCHCH9, 10, 11 All 3tOSC3tOSCns CLKOUT high time tCHCL9, 10, 11 All 3tOSC- 35 3tOSC+ 10 ns CLKOUT low to ALE high tCLLH9, 10, 11 All -30.0 +15.0 ns ALE/ADV low to CLKOUT high tLLCH9, 10, 11 All tOSC- 25 tOSC+ 45 ns ALE/ADV high time 9/ tLHLL9, 10, 11 All tOSC 30 9/ tOSC+ 35 9/ ns Address setup to end of ALE/ADV 7/ tAVLL9, 10, 11