ImageVerifierCode 换一换
格式:PDF , 页数:13 ,大小:91.13KB ,
资源ID:698882      下载积分:10000 积分
快捷下载
登录下载
邮箱/手机:
温馨提示:
如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
如填写123,账号就是123,密码也是123。
特别说明:
请自助下载,系统不会自动发送文件的哦; 如果您已付费,想二次下载,请登录后访问:我的下载记录
支付方式: 支付宝扫码支付 微信扫码支付   
注意:如需开发票,请勿充值!
验证码:   换一换

加入VIP,免费下载
 

温馨提示:由于个人手机设置不同,如果发现不能下载,请复制以下地址【http://www.mydoc123.com/d-698882.html】到电脑端继续下载(重复下载不扣费)。

已注册用户请登录:
账号:
密码:
验证码:   换一换
  忘记密码?
三方登录: 微信登录  

下载须知

1: 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。
2: 试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。
3: 文件的所有权益归上传用户所有。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 本站仅提供交流平台,并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

版权提示 | 免责声明

本文(DLA SMD-5962-86812 REV D-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS HEX BUFFER DRIVER WITH INVERTING THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf)为本站会员(testyield361)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-86812 REV D-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS HEX BUFFER DRIVER WITH INVERTING THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change figure 3. Editorial changes. 87-03-31 N. A. Hauck B Add vendor CAGE code 27014 to case outline 012X. Inactivate for new design, case outline 01EX. 87-11-18 R. P. Evans C Add test circuit and notes in figure 4. Update boilerplate to MIL-PRF

2、-38535 requirements. Editorial changes throughout. - LTG04-05-28 Thomas M. Hess D Correct the conditions IOHand IOLfor output voltage tests in table I. Editorial changes throughout. - jak 11-03-15 David Corbett CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEET

3、S SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, DIGITAL, HIGH

4、SPEED CMOS, HEX BUFFER/DRIVER WITH INVERTING THREE- STATE OUTPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-09-26 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 5962-86812 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E141-11 Provided by IHSNot for ResaleNo

5、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, n

6、on-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86812 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). T

7、he device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC368 Hex buffer/driver with inverting three-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator T

8、erminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5

9、V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 35 mA VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 500 mW 3/ Lead temperature (soldering 10 s

10、econds) . 260C Thermal resistance, junction-to-case (JC): Cases E and 2 See MIL-STD-1835 Junction temperature (TJ) 175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC=

11、 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are ref

12、erenced to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FO

13、RM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitati

14、on or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEF

15、ENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelph

16、ia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD

17、7-A - Standard for Description of 54/74HCXXXX and 54/74HCTXXXX High-Speed CMOS Devices (Copies of these documents are available online at http:/www.jedec.org/ or by mailing to, JEDEC, 3103 North 10thstreet suite 240-S, Arlington, VA 22201-2107.) 2.3 Order of precedence. In the event of a conflict be

18、tween the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requireme

19、nts shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certi

20、fication to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. T

21、hese modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physi

22、cal dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. Pr

23、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2.3 Truth table. The truth table shall be as specified on f

24、igure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical per

25、formance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 M

26、arking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

27、 has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in

28、accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted

29、 to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appen

30、dix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s ag

31、ent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

32、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Li

33、mits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 All 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -6.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -7.8 mA VCC= 6.0 V 5.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 All 0.1 V VCC

34、= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +6.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +7.8 mA VCC= 6.0 V 0.4 High level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 All 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 All 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent

35、 supply current ICCVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Input capacitance CINVIN= 0.0 V, TC= 25C See 4.3.1c 4 All 10.0 pF Output capacitance COUTVOUT= 0.0 V, TC= 25C See 4.3.1c 4 All 20.0 pF Three-state output current IOZV

36、IN= VIHor VIL, VOUT= VCCor GND 1, 2, 3 All 10.0 A Functional tests See 4.3.1d 7 All L H Propagation delay time, A to Y tPHL, tPLH3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 125 ns VCC= 4.5 V 25 VCC= 6.0 V 21 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 190 ns VCC= 4.5

37、V 38 VCC= 6.0 V 32 Propagation delay time, output disable, OE to Y tPLZ, tPHZ3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 175 ns VCC= 4.5 V 35 VCC= 6.0 V 31 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 265 ns VCC= 4.5 V 53 VCC= 6.0 V 46 See footnotes at end of table. Pr

38、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Te

39、st Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Propagation delay time, output enable, OE to Y tPZL, tPZH 3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 190 ns VCC= 4.5 V 38 VCC= 6.0 V 35 TC= -55C, +125C CL= 50 pF 10% See figu

40、re 4 VCC= 2.0 V 10, 11 All 285 ns VCC= 4.5 V 57 VCC= 6.0 V 52 Transition time tTHL, tTLH4/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 60 ns VCC= 4.5 V 12 VCC= 6.0 V 10 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 90 ns VCC= 4.5 V 18 VCC= 6.0 V 15 1/ For a power supply of

41、 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IIN, ICC, and IO

42、Z) occur for CMOS at the higher voltage and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 45 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ Tests not required if appl

43、ied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified limits. 4/ Transition times, if not tested, shall be guaranteed to the specified limits. Provided by IHSNot for ResaleNo reproduction or networking permitted with

44、out license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E 2 Terminal number Terminal symbol Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

45、1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND 1Y4 1A4 2Y1 2A1 2Y2 2A2 2OE VCC- - - - NC 1OE 1A1 1Y1 1A2 NC 1Y2 1A3 1Y3 GND NC 1Y4 1A4 2Y1 2A1 NC 2Y2 2A2 2OE VCCNC = No internal connection FIGURE 1. Terminal connections. Each buffer/driver Inputs Outputs OE A Y L L H L H L H X Z H = High voltage level L = Low volt

46、age level X = Irrelevant Z = High impedance FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234

47、 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Switching wavefo

48、rms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86812 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 PARAMETER RLCLS1 S2 tPZH 1k 50 pF Open Closed tPZLClosed OpentPHZ1k 50 pF Open Closed tPLZClosed OpentPLH, tPHLor

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1