DLA SMD-5962-86813 REV C-2008 MICROCIRCUIT DIGITAL HIGH SPEED CMOS OCTAL D-TYPE LATCH WITH THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor 27014 for device types 01RX and 012X. 87-03-25 C. Reusing B Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 03-05-15 Thomas M. Hess C Update boilerplate to MIL-PRF-38535 requirements. - LTG 08-11-19

2、Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Greg A. Pitz CHECKED BY D. A. DiCenzo DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Charles Reusing

3、 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-09-08 MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, OCTAL D-TYPE LATCH WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE C

4、ODE 14933 5962-86813 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E047-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DS

5、CC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86813 01 R

6、 A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC533 Octal D-type latch with three-state outputs 1.2.2 Case outline(s). The cas

7、e outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maxim

8、um ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 35 mA VCCor GND current (per pin) . 70 mA Storage temperature ran

9、ge (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ . 500 mW Lead temperature (soldering 10 seconds) . 260C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Junction temperature (TJ) 175C 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +12

10、5C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended op

11、erating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC). -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V. 0 to 1000 ns VCC= 4.5 V. 0 to 500 ns VCC= 6.0 V. 0 to 400 ns Minimum setup time, input D to latch enable (tS): TC= +25C: VCC= 2.0 V

12、. 100 ns VCC= 4.5 V. 20 ns VCC= 6.0 V. 17 ns TC= -55C to +125C: VCC= 2.0 V. 150 ns VCC= 4.5 V. 30 ns VCC= 6.0 V. 26 ns Minimum latch enable pulse width (tW): TC= +25C: VCC= 2.0 V. 100 ns VCC= 4.5 V. 20 ns VCC= 6.0 V. 17 ns TC= -55C to +125C: VCC= 2.0 V. 150 ns VCC= 4.5 V. 30 ns VCC= 6.0 V. 26 ns Min

13、imum hold time, latch enable to input D (tH): TC= +25C: VCC= 2.0 V. 50 ns VCC= 4.5 V. 10 ns VCC= 6.0 V. 10 ns TC= -55C to +125C: VCC= 2.0 V. 75 ns VCC= 4.5 V. 20 ns VCC= 6.0 V. 20 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standard

14、s, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. D

15、EPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of thes

16、e documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

17、IRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. No

18、thing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

19、herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved progr

20、am plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affec

21、t the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, app

22、endix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagra

23、m shall be as specified on figure 3. 3.2.5 Switching waveforms. The switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the fu

24、ll case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part

25、shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/co

26、mpliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6

27、Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that t

28、he manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification

29、 of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation sh

30、all be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2

31、234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC+125C unless otherwise specified Min Max VCC= 2.0 V 1.9 VCC= 4.5 V 4.4 VIN= VIHor VILIO 20 A VCC= 6.0 V 5.9 VIN= VIHor VILIO 6.0 mA VCC= 4.5 V 3.7 High level output

32、voltage VOHVIN= VIHor VILIO 7.8 mA VCC= 6.0 V 1, 2, 3 All 5.2 V VCC= 2.0 V 0.1 VCC= 4.5 V 0.1 VIN= VIHor VILIO 20 A VCC= 6.0 V 0.1 VIN= VIHor VILIO 6.0 mA VCC= 4.5 V 0.4 Low level output voltage VOLVIN= VIHor VILIO 7.8 mA VCC= 6.0 V 1, 2, 3 All 0.4 V VCC= 2.0 V 1.5 VCC= 4.5 V 3.15 High level input v

33、oltage 2/ VIHVCC= 6.0 V 1, 2, 3 All 4.2 V VCC= 2.0 V 0.3 VCC= 4.5 V 0.9 Low level input voltage 2/ VILVCC= 6.0 V 1, 2, 3 All 1.2 V Quiescent current ICCVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Input capacitance CINVIN= 0.0 V,

34、TC= 25C See 4.3.1c 4 All 10.0 pF Output capacitance COUTVOUT= 0.0 V, TC= 25C, See 4.3.1c 4 All 20 pF Three-state output current IOZVIN= VIHor VILVOUT= VCCor GND 1, 2, 3 All 10.0 A Functional tests See 4.3.1d 7 All L H VCC= 2.0 V 165 VCC= 4.5 V 33 TC= 25C CL= 50 pF 10% See figure 4 VCC= 6.0 V 9 All 2

35、8 ns VCC= 2.0 V 250 VCC= 4.5 V 50 Propagation delay time, input D to Q 3/ tPHL1, tPLH1TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 6.0 V 10, 11 All 43 ns VCC= 2.0 V 175 VCC= 4.5 V 35 TC= 25C CL= 50 pF 10% See figure 4 VCC= 6.0 V 9 All 30 ns VCC= 2.0 V 265 VCC= 4.5 V 53 Propagation delay time, lat

36、ch enable to Q 3/ tPHL2, tPLH2TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 6.0 V 10, 11 All 45 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER

37、COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC+125C unless otherwise specified Min Max VCC= 2.0 V 150 VCC= 4.5 V 30 TC= 25C CL= 50

38、 pF 10% See figure 4 VCC= 6.0 V 9 All 26 ns VCC= 2.0 V 225 VCC= 4.5 V 45 Propagation delay time, output disable, OE to Q 3/ tPLZ, tPHZTC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 6.0 V 10, 11 All 39 ns VCC= 2.0 V 150 VCC= 4.5 V 30 TC= 25C CL= 50 pF 10% See figure 4 VCC= 6.0 V 9 All 26 ns VCC= 2.0

39、 V 225 VCC= 4.5 V 45 Propagation delay time, output enable, OE to Q 3/ tPZL, tPZHTC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 6.0 V 10, 11 All 39 ns VCC= 2.0 V 60 VCC= 4.5 V 12 TC= 25C CL= 50 pF 10% See figure 4 VCC= 6.0 V 9 All 10 ns VCC= 2.0 V 90 VCC= 4.5 V 18 Transition time 4/ tTHL, tTLHTC= -

40、55C, +125C CL= 50 pF 10% See figure 4 VCC= 6.0 V 10, 11 All 15 ns 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respecti

41、vely. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 50 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and

42、 the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ Tests not required if applied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified parameters. 4/ Transition times, if not tested, shall be guaranteed to t

43、he specified parameters. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outli

44、nes R and 2 Terminal numbers Terminal symbols 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND LE Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCCFIGURE 1. Terminal connections. Inputs Outputs OE LE D Q L H H L L H L L X no change H X Z H = High voltage level L = Low voltage level X = Ir

45、relevant Z = High impedance FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97

46、 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Switching wave

47、forms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86813 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspectio

48、n. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C or D. The test circuit shall be ma