DLA SMD-5962-86814 REV C-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS OCTAL D-TYPE FLIP-FLOP MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE number 27014 to case outline 2. Editorial changes in figures 1, 2, 3, and 4. Change drawing CAGE to 67268. 87-07-29 N. A. Hauck B Add test circuit and notes to figure 4. Update boilerplate to MIL-PRF-38535 requirements. Editorial

2、changes throughout. LTG 04-04-15 Thomas M. Hess C Correct the conditions IOHand IOLfor output voltage tests in table I. Editorial changes throughout. - jak 11-03-15 David Corbett REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARE

3、D BY Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Robert P. Evans MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, OCTAL D-TYPE FLIP-FLOP, MONOLITHIC

4、SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 86-09-16 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-86814 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E142-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

5、ROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix

6、A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86814 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generi

7、c number Circuit function 01 54HC534 Octal D-type, flip-flop with inverting three-state outputs1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N

8、20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+

9、0.5 V dc Clamp diode current 20 mA DC output current (per pin) 35 mA VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) . 500 mW 3/ Lead temperature (soldering 10 seconds) . 260C Thermal resistance, junction-to-case (JC): Cases R and 2

10、 . See MIL-STD-1835 Junction temperature (TJ) 175C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Reco

11、mmended operating conditions. Supply voltage range (VCC) . +2.0 V dc to +6.0 V dc Case operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns Minimum setup time, input D to clock (tS): TC= +25C: VCC= 2.0

12、V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to +125C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum clock pulse width (tW): TC= +25C: VCC= 2.0 V 80 ns VCC= 4.5 V 16 ns VCC= 6.0 V 14 ns TC= -55C to +125C: VCC= 2.0 V 120 ns VCC= 4.5 V 24 ns VCC= 6.0 V 20 ns Minimum hold time, clo

13、ck to input D (tH): TC= +25C: VCC= 2.0 V 50 ns VCC= 4.5 V 10 ns VCC= 6.0 V 9 ns TC= -55C to +125C: VCC= 2.0 V 75 ns VCC= 4.5 V 15 ns VCC= 6.0 V 13 ns Maximum clock frequency (fMAX): TC= +25C: VCC= 2.0 V 6 MHz VCC= 4.5 V 30 MHz VCC= 6.0 V 35 MHz TC= -55C to +125C: VCC= 2.0 V 4 MHz VCC= 4.5 V 20 MHz V

14、CC= 6.0 V 23 MHz 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the Maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ For TC= +100C to +125C, derate li

15、nearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government s

16、pecification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL

17、-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcir

18、cuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. Th

19、e following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7-A - Standard for Description of 54/74H

20、CXXXX and 54/74HCTXXXX High-Speed CMOS Devices (Copies of these documents are available online at http:/www.jedec.org/ or by mailing to, JEDEC, 3103 North 10thstreet suite 240-S, Arlington, VA 22201-2107.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the r

21、eferences cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-

22、38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be process

23、ed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form

24、, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction

25、, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall b

26、e as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic

27、diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specifie

28、d in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance w

29、ith MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962

30、-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identif

31、y when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to li

32、sting as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of

33、microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the

34、option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZ

35、E A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage

36、 VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 All 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -6.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -7.8 mA VCC= 6.0 V 5.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 All 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIO

37、L= +6.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +7.8 mA VCC= 6.0 V 0.4 High level input voltage VIH2/ VCC= 2.0 V 1, 2, 3 All 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input voltage VIL2/ VCC= 2.0 V 1, 2, 3 All 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent supply current ICCVCC= 6.0 V, VIN= VCCor G

38、ND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Input capacitance CINVIN= 0.0 V, TC= 25C See 4.3.1c 4 All 10.0 pF Output capacitance COUTVOUT= 0.0 V, TC= 25C See 4.3.1c 4 All 20.0 pF Three-state output current IOZVIN= VIHor VILVOUT= VCCor GND 1, 2, 3 All 10

39、.0 A Functional tests See 4.3.1d 7 All L H Propagation delay time, clock to Q tPHL, tPLH3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 180 ns VCC= 4.5 V 36 VCC= 6.0 V 31 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 270 ns VCC= 4.5 V 54 VCC= 6.0 V 46 Propagation delay time

40、, output disable, OE to Q tPLZ, tPHZ3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 150 ns VCC= 4.5 V 30 VCC= 6.0 V 26 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 225 ns VCC= 4.5 V 45 VCC= 6.0 V 39 See footnotes at end of table. Provided by IHSNot for ResaleNo reproductio

41、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC+125C unle

42、ss otherwise specified Group A subgroups Device type Limits Unit Min Max Propagation delay time, output enable, OE to Q tPZL, tPZH3/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 175 ns VCC= 4.5 V 35 VCC= 6.0 V 30 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 265 ns VCC= 4.5

43、 V 53 VCC= 6.0 V 45 Transition time tTHL, tTLH4/ TC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 60 ns VCC= 4.5 V 12 VCC= 6.0 V 10 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 90 ns VCC= 4.5 V 18 VCC= 6.0 V 15 1/ For a power supply of 5.0 V 10%, the worst case output voltages

44、 (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage an

45、d so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 50 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ Tests not required if applied as a forcing function for VOHand VOL.

46、3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified parameters. 4/ Transition times, if not tested, shall be guaranteed to the specified parameters. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

47、MICROCIRCUIT DRAWING SIZE A 5962-86814 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines R and 2 Terminal numbers Terminal symbols 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND CLOCK Q4 D4 D

48、5 Q5 Q6 D6 D7 Q7 VCCFIGURE 1. Terminal connections. Inputs Outputs OE CLOCK D Q L H L L L H L L X no change H X X Z H = High voltage level L = Low voltage level X = Irrelevant Z = High impedance = Low-to-high transition FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5