DLA SMD-5962-86824 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS 4-BIT SYNCHRONOUS DECADE COUNTER MONOLITHIC SILICON.pdf

1、6 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE 27014 to case outline 2. Add Clear input to truth table. Editorial changes throughout. Add vendor CAGE 01295 to case outline F. 87-04-10 Nelson A. Hauck B Correct the title. Correct the conditions for VOHand VOLtests in table I.

2、Editorial changes throughout . - jak 12-02-02 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Jeffery Tunstall DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmarit

3、ime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Dan DiCenzo THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Nelson A. Hauck MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, 4-BIT SYNCHRONOUS DECADE COUNTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 86-09-29 AMSC N/A REVISION LEVEL B SIZE

4、 A CAGE CODE 14933 5962-86824 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E110-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 2 DS

5、CC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86824 01 E

6、 A_ Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC160 4-Bit synchronous decade counter 1.2.2 Case outline(s). The case outli

7、ne(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-P

8、RF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+0.5 V dc Input clamp current (IIK) . 20 mA Output clamp current (IOK) . 20 mA DC output

9、 current (per pin) . 25 mA DC VCCor GND current (per pin) 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD): 500 mW 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 R

10、ecommended operating conditions. 2/ Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns 1/ Stresses above the absolute maximum rating may cause pe

11、rmanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to GND. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking

12、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards

13、, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DE

14、PARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these

15、 documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified h

16、erein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD-7-A - Standard for Description of 54/74HCXXXX and 54/74HCTXXXX High-Speed CMOS Devices. (Copies of these documents are available onl

17、ine at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Noth

18、ing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified he

19、rein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program

20、 plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect

21、the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appen

22、dix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The

23、 logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms. The switching waveforms and test circuit shall be as specified in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITI

24、ME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature

25、 range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN

26、listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance i

27、ndicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A

28、certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufact

29、urers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change.

30、 Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required

31、 documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 40 (see MIL-PRF-38535, appendix A). Provided by IHSNot for

32、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -

33、55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max High level output voltage VOHVIN= VIHor VILIOH -20 A VCC= 2.0 V 1, 2, 3 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH -4.0 mA VCC= 4.5 V 1, 2, 3 3.70 VIN= VIHor VILIOH -5.2 mA VCC= 6.0 V 1, 2, 3 5.20 Low level outp

34、ut voltage VOLVIN= VIHor VILIOL +20 A VCC= 2.0 V 1, 2, 3 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL +4.0 mA VCC= 4.5 V 1, 2, 3 0.4 VIN= VIHor VILIOL +5.2 mA VCC= 6.0 V 1, 2, 3 0.4 High level input voltage VIH 2/ VCC= 2.0 V 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input volta

35、ge VIL 2/ VCC= 2.0 V 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Input capacitance CINVIN= 0.0 V TC= +25C See 4.4.1c 4 10.0 pF Quiescent supply current ICCVIN = VCC or GND VCC= 6.0 V 1, 2, 3 160.0 A Input leakage current IINVCC= 6.0 V VIN= VCCor GND 1, 2, 3 1.0 A See footnotes at end of table. Provi

36、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Tes

37、t Symbol Test conditions 1/ -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Functional tests See 4.4.1b 7 Propagation delay time, CLOCK to Q tPHL1, tPLH1 3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 205 ns VCC= 4.5 V 41 VCC= 6.0 V 35 TC= -55C, +125C CL= 50 pF 10

38、% See figure 4 VCC= 2.0 V 10, 11 310 ns VCC= 4.5 V 62 VCC= 6.0 V 53 Propagation delay time, RESET to Q tPHL2 3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 225 ns VCC= 4.5 V 45 VCC= 6.0 V 38 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 340 ns VCC= 4.5 V 68 VCC= 6.0 V 58 Propagat

39、ion delay time, ENABLE T to RIPPLE CARRY OUT tPHL3, tPLH3 3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 195 ns VCC= 4.5 V 39 VCC= 6.0 V 33 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 295 ns VCC= 4.5 V 59 VCC= 6.0 V 50 See footnotes at end of table. Provided by IHSNot for Resal

40、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition

41、s 1/ -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Propagation delay time, CLOCK to RIPPLE CARRY OUT tPHL4, tPLH4 3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 215 ns VCC= 4.5 V 43 VCC= 6.0 V 37 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 325 n

42、s VCC= 4.5 V 65 VCC= 6.0 V 55 Propagation delay time, RESET to RIPPLE CARRY OUT tPHL5 3/ TC= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 220 ns VCC= 4.5 V 44 VCC= 6.0 V 37 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 330 ns VCC= 4.5 V 66 VCC= 6.0 V 56 Transition time tTLH tTHL 4/ TC

43、= +25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 75 ns VCC= 4.5 V 15 VCC= 6.0 V 13 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 110 ns VCC= 4.5 V 22 VCC= 6.0 V 19 1/ For a power supply of 5 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values

44、 should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. (The VIHvalue at 5.5 V is 3.85 V.) The worst case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage, so the 6.0 V values should be used. Power dissipation capaci

45、tance (CPD), typically 45 pF per latch, determines the no load dynamic power consumption, PD= (CPDVCC2f) + (ICCVCC), and the no load dynamic current consumption, IS= CPDVCC f + ICC. 2/ VIHand VILtests are not required and shall be applied as forcing functions for the VOHor VOLtests. 3/ AC testing at

46、 VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified limits. 4/ Transition time (tTLH, tTHL), if not tested, shall be guaranteed to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

47、ICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-86824 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case Outline E, F 2 Terminal Number Terminal Symbol Terminal Symbol 1 RESETNC 2 CLOCK RESET3 P0 CLOCK 4 P1 P0 5 P2 P1 6 P3 NC 7 ENABLE P P2 8 GND P3 9 L

48、OADENABLE P 10 ENABLE T GND 11 Q3NC 12 Q2LOAD 13 Q1ENABLE T 14 Q0 Q315 RIPPLE CARRY OUT Q216 VCC NC17 - - - Q118 - - - Q0 19 - - - RIPPLE CARRY OUT 20 - - - VCC NC = No internal connection FIGURE 1. Terminal connections. INPUTS OUTPUTS CLEAR CLOCKLOAD ENABLE P ENABLE T Q L X X X X REST H L X X LOAD RESET DATA H H H H COUNT H X H L X NO COUNT H X H X L NO COUNT H = High voltage level. L = Low voltage level. X = Irrelevant. = CLOCK transition fr