DLA SMD-5962-86828 REV D-2010 MICROCIRCUIT DIGITAL HIGH SPEED CMOS HEX BUFFER DRIVER WITH INVERTING THREE-STATE OUTPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE 27014 to case outline 2. 87-09-23 N. A. Hauck B Add vendor CAGE 01295 to case outlines E and 2. Editorial changes throughout. 88-03-15 M. A. Frye C Add test circuit and notes in figure 4. Update boilerplate to MIL-PRF-38535 requir

2、ements. Editorial changes throughout. - LTG 04-06-18 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 10-11-22 Thomas M. Hess CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMI

3、C N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY M. A. Frye MICROCIRCU

4、IT, DIGITAL, HIGH SPEED CMOS, HEX BUFFER/DRIVER WITH INVERTING THREE- STATE OUTPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 86-09-22 REVISION LEVEL D SIZE A CAGE CODE 14933 5962-86828 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E088-11 Provided by IHSNot for ResaleNo reproduction or networking permit

5、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuit

6、s in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86828 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the ci

7、rcuit function as follows: Device type Generic number Circuit function 01 54HC366 Hex buffer/driver with inverting three-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T1

8、6 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output volt

9、age range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 35 mA VCCor GND current (per pin) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ . 500 mW Lead temperature (soldering 10 seconds) . 260C Thermal resistance,

10、 junction-to-case (JC): Cases E and 2 See MIL-STD-1835 Junction temperature (TJ) 175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Case operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V .

11、 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 59

12、62-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Un

13、less otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits

14、. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or

15、from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the

16、solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 7-A - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from Electronic Industries Alliance, 2500 Wilson Boule

17、vard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption

18、has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certifi

19、ed and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented i

20、n the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is req

21、uired to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

22、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be

23、as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electr

24、ical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full (case or ambient) operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the sub

25、groups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages w

26、here marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, a

27、ppendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an

28、 approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herei

29、n. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that af

30、fects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the

31、reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics.

32、Test Symbol Test conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 All 1.9 V VCC= 4.5 V 4.4 VCC= 6.0 V 5.9 VIN= VIHor VILIOH= -6.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -7.8

33、mA VCC= 6.0 V 5.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 All 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +6.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +7.8 mA VCC= 6.0 V 0.4 High level input voltage 2/ VIHVCC= 2.0 V 1, 2, 3 All 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V

34、 4.2 Low level input voltage 2/ VILVCC= 2.0 V 1, 2, 3 All 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent supply current ICCVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Input capacitance CINVIN= 0.0 V, TC= 25C See 4.3.1c 4 All 10.0

35、pF Three-state output current IOZVIN= VIHor VILVOUT= VCCor GND 1, 2, 3 All 10.0 A Functional tests See 4.3.1d 7 All L H Propagation delay time, A to Y 3/ tPHL, tPLHTC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 125 ns VCC= 4.5 V 25 VCC= 6.0 V 21 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2

36、.0 V 10, 11 All 190 ns VCC= 4.5 V 38 VCC= 6.0 V 32 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6

37、 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Propagation delay time, output disable, OE to Y 3/ tPLZ, tPHZTC= 25C CL= 50 pF 10% See figure 4 V

38、CC= 2.0 V 9 All 220 ns VCC= 4.5 V 44 VCC= 6.0 V 37 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 330 ns VCC= 4.5 V 66 VCC= 6.0 V 56 Propagation delay time, output enable, OE to Y 3/ tPZL, tPZHTC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 230 ns VCC= 4.5 V 44 VCC= 6.0 V 37 TC

39、= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 345 ns VCC= 4.5 V 66 VCC= 6.0 V 56 Transition time 4/ tTHL, tTLHTC= 25C CL= 50 pF 10% See figure 4 VCC= 2.0 V 9 All 60 ns VCC= 4.5 V 12 VCC= 6.0 V 10 TC= -55C, +125C CL= 50 pF 10% See figure 4 VCC= 2.0 V 10, 11 All 90 ns VCC= 4.5 V 18 VC

40、C= 6.0 V 15 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at 5.5 V is 3.85 V). The worst cas

41、e leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 45 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf

42、+ ICC. 2/ Tests not required if applied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified limits. 4/ Transition times, if not tested, shall be guaranteed to the specified limits. Provided by IHSNot for ResaleNo repro

43、duction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E 2 Terminal number Terminal symbol Terminal symbol 1 2 3 4 5 6 7 8

44、 9 10 11 12 13 14 15 16 17 18 19 20 OE1 A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 OE2 VCC- - - - NC OE1 A1 Y1 A2 NC Y2 A3 Y3 GND NC Y4 A4 Y5 A5 NC Y6 A6 OE2 VCCNC = No internal connection FIGURE 1. Terminal connections. Inputs Outputs OE1 OE2 A Y L L L H L L H L H X X Z X H X Z H = High voltage level

45、L = Low voltage level X = Irrelevant Z = High impedance FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DS

46、CC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Swit

47、ching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86828 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 Parameter RLCLS1 S2 tPZH

48、 1k 50 pF Open Closed tPZLClosed OpentPHZ1k 50 pF Open Closed tPLZClosed OpentPLH, tPHLor tTHL, tTLH- 50 pF Open Open NOTES: 1. CLincludes test jig and probe capacitance. 2 Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. Input signal from pulse generator: VIN= 0.0 V to VCC; PRR