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本文(DLA SMD-5962-86859 REV B-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 16K X 4 SRAM MONOLITHIC SILICON《硅单块 互补金属氧化物半导体16比特X4静态随机存取存储器数字主体储存器微型电路》.pdf)为本站会员(arrownail386)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-86859 REV B-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 16K X 4 SRAM MONOLITHIC SILICON《硅单块 互补金属氧化物半导体16比特X4静态随机存取存储器数字主体储存器微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R015-92 91-10-22 Michael A. Frye B Boilerplate update, part of 5 year review. ksr 06-07-21 Raymond Monnin REV SHET REV B B B B B B SHEET 15 16 17 18 19 20 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SH

2、EET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES

3、 OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-06-20 MICROCIRCUIT, MEMORY, DIGITAL, CMOS 16K X 4 SRAM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-86859 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E529-06 .Provided by IHSNot for ResaleNo reproduction or networking p

4、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level

5、B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86859 01 L A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) i

6、dentify the circuit function as follows: Device type Generic number Circuit function Access time 01 85 ns 02 03 70 ns 04 05 55 ns 06 07 45 ns 08 09 35 ns 10 11 See 6.4 16K X 4 Static Ram 70 ns 12 70 ns 13 55 14 ns 15 45 16 ns 17 35 18 ns 19 55 20 ns 21 45 22 ns 23 35 24 ns 1.2.2 Case outline(s). The

7、 case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package L GDIP3-T24 or CDIP4-T24 24 dual-in-line package T See Figure 1 22 dual-in-line package U CQCC4-N28 28 leadless chip carrier packa

8、ge W GDIP1-T22 or CDIP2-T22 22 dual-in-line package X CQCC3-N28 28 leadless chip carrier package Y See Figure 1 22 dual-in-line package Z See Figure 1 22 leadless chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo rep

9、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) .-0.5 V dc to +7.0 V dc 1

10、/ DC output current20 mA Ambient storage temperature-65C to +150C Temperature under bias-55C to +125C Thermal resistance, junction-to-case (JC): Cases K, L, U, W, and X .See MIL-STD-1835 Cases Y and T 28C/W 2/ Cases Z.22C/W 2/ Power dissipation (PD) 1.0 W 1.4 Recommended operating conditions. Supply

11、 voltage (VCC) .+4.5 V dc to +5.5 V dc 1/ Ground voltage (VSS) 0 V dc Input high voltage (VIH)+2.2 V dc to VCC+ 0.5 V dc Input low voltage (VIL) .-0.5 V dc to .8 V dc 3/ Operating case temperature range (TC)-55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.

12、 The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manuf

13、acturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard

14、Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a con

15、flict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ All voltage referenced to VSS. 2/ When a thermal resist

16、ance value is included in MIL-STD-1835, it shall supersede the value stated herein. 3/ VILnegative undershoots to a minimum of -2.0 V dc are allowed with a maximum 20 ns pulse width. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU

17、IT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as

18、specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers appr

19、oved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall

20、 not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-

21、38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth tables. The truth tables shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.4 Die overco

22、at. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of M

23、IL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance

24、 characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II.

25、 The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SM

26、D PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance ind

27、icator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in

28、 MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certifica

29、te of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs ag

30、ent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

31、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2

32、 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall b

33、e maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method

34、1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformanc

35、e inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5, and 6 in table I, method 5005 of MIL-STD-883 sh

36、all be omitted. c. Subgroup 4 (CIand COmeasurement) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15

37、devices with no failures, and all input and output terminals tested. d. Subgroups 7, 8A, and 8B shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1

38、005 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipa

39、tion, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with M

40、IL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical perf

41、ormance characteristics. Limits Test Symbol Conditions -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit Input leakage current ILIVCC= max, VIN= GND to VCC1, 2, 3 All 10 A Output leakage current ILOVCC= max, VOUT= GND to VCCCE VIHWE VIL1, 2

42、, 3 All 10 A Output low voltage VOLVCC= 4.5 V, IOL= 8 mA VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 0.4 V Output high voltage VOHVCC= 4.5 V, IOH= -4 mA VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 2.4 V 01, 03, 05, 07, 09 140 02, 04, 06, 08, 10, 17, 18, 23, 24 115 Operating supply current ICC1CE = VIL, outputs open V

43、CC= max, f = 1/tAVAX1, 2, 3 11-16, 19-22 90 mA 01-10 50 Standby power supply current (TTL) ICC2CE VIH, outputs open VCC= max 1, 2, 3 11-24 30 mA Standby power supply current (CMOS) ICC3VCC+ 0.2 V CE VCC- 0.2 V outputs open VCC+ 0.2 V VIN VCC- 0.2 V or +0.2 V VIN -0.2 V 1, 2, 3 All 25 mA Data retenti

44、on current ICC41/ VCC= VDR= 2.0 V 1, 2, 3 02, 04, 06, 08, 10, 11, 13, 15, 17, 19, 21, 23 1000 A Input capacitance CI1/ VI= 5.0 V or GND f = 1 MHz, TC= +25C See 4.3.1c 4 All 8 pF Output capacitance CO1/ VO= 5.0 V or GND f = 1 MHz, TC= +25C See 4.3.1c 4 All 10 pF See footnotes at end of table. Provide

45、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continu

46、ed. Limits Test Symbol Conditions 3/ 4/ -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Min Max Unit 01, 02 85 03, 04, 11, 12 70 05, 06, 13, 14, 19, 20 55 07, 08, 15, 16, 21, 22 45 Read cycle time tAVAX1/ 2/ 9, 10, 11 09, 10, 17, 18, 23, 24 35 ns 01,

47、02 85 03, 04, 11, 12 70 05, 06, 13, 14, 19, 20 55 07, 08, 15, 16, 21, 22 45 Address cycle time tAVQV2/ 9, 10, 11 09, 10, 17, 18, 23, 24 35 ns 01, 02 85 03, 04, 11, 12 70 05, 06, 13, 14, 19, 20 55 07, 08, 15, 16, 21, 22 45 Chip-enable access time tELQV1/ 2/ 9, 10, 11 09, 10, 17, 18, 23, 24 35 ns Outp

48、ut hold from address change tAVQX1/ 2/ 9, 10, 11 All 3 ns Chip select to power up time tPU5/ 9, 10, 11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86859 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 3/ 4/ -55C TC +125C VSS= 0 V, 4.5 V VCC 5.5

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