DLA SMD-5962-86864 REV A-2010 MICROCIRCUIT MEMORY DIGITAL CMOS ULTRAVIOLET ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. ksr. 10-08-24 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED REV SHET REV A A A SHET 15 16 17 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS

2、SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick Officer DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Dan DiCenzo MICROCIRCUIT, MEMORY, DIGIT

3、AL, CMOS, ULTRAVIOLET ERASABLE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88 08 - 26 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-86864 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E324-10 .Provided by IHSNot for ResaleNo reprod

4、uction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN

5、 class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86864 01 L A _ Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). Th

6、e device type(s) identify the circuit function as follows: Device type Generic number Circuit function Address access time 01 600 gate EPLD 55 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style

7、 L CDIP4-T24 or GDIP3-T24 24 dual-in-line package 1/ X See figure 1 28 J leaded chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VCC) - -2.0 V dc to +7.0 V dc Programming supply voltage (VPP)- -2.0 V

8、dc to +13.5 V dc DC Input voltage (VI) 2/ - - -0.5 V dc to VCC+ 0.3 V dc Power dissipation (PD) - 650 mW Storage temperature range - -65C to +150C Junction temperature (TJ) - +200C Thermal resistance, junction-to-case (JC) : Case L - See MIL-STD-1835 Case X - 20C/W 3/ DC supply current, (ICCor ISS)

9、- + 100 mA DC output current, (IO) per pin - + 25 mA 1.4 Recommended operating conditions. Supply voltage range (VCC) - +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) - -0.3 V dc to +0.8 V dc Minimum high level input voltage (VIH) - +2.0 V dc to VCC+ 0.3 V dc Case operating temperature

10、 range (TC) - -55C to +125C Input rise time (TR) - 500 ns maximum Input fall time (TF) - 500 ns maximum Clock pins, rise time - 100 ns maximum Clock pins, fall time - 100 ns maximum _ 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Minimum dc input voltage is -0.5 V dc. During tr

11、ansitions the inputs may undershoot to -2.0 V dc for periods less than 20 ns under no load conditions. 3/ When a thermal resistance values is included in MIL-M-38510, appendix C, it shall supersede the value stated herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without

12、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks fo

13、rm a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENS

14、E STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are ava

15、ilable online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of t

16、his drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class l

17、evel B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with

18、the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. The

19、se modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as

20、 specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified

21、 on figure 3. 3.2.3.1 Unprogrammed or erased device. The truth table for unprogrammed devices shall be as specified on figure 3. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.3 Electrical performance characteristics. Unless otherwise sp

22、ecified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range with the low standby power mode disabled. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table

23、 II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2

24、234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations,

25、the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certif

26、ication mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPLDS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPLDS. When specified, devices shall be erased

27、 in accordance with the procedures and characteristics specified in 4.4. 3.6.2 Programmability of EPLDS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 and table III. 3.6.3 Verification of erasure of programmability of E

28、PLDS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall

29、 constitute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Lan

30、d and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall

31、be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.10 Verification and review. DLA Land and Maritime-VA, DLA Land and Maritimes -VA agent, a

32、nd the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-

33、,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Test Symbol Conditions 1/ -55C TC+125C VCC= 4.5 V dc to 5.5 V dc (unless otherwise specified) Device type

34、 Group A subgroups Limits Unit Min Max High level input voltage VIH01 1, 2, 3 2.0 VCC+0.3 2/ V Low level input voltage VIL01 1, 2, 3 2/ -0.3 0.8 V Low level ouput voltage VOLIOL= 4.0 mA 01 1, 2, 3 0.45 V High level TTL output voltage VOH(TTL) IOH= -4.0 mA 01 1, 2, 3 2.4 V High level CMOS output volt

35、age VOH(CMOS) IOH= -2.0 mA 01 1, 2, 3 3.84 V Input leakage current IIVI= VCCor GND 01 1, 2, 3 -10 10 A 3-state output off current IOZVO= VCCor GND 01 1, 2, 3 -10 10 A VCCsupply current 3/ ICCVIN= 0 V or VCCf = 1.0 MHz 01 1, 2, 3 60 mA Input capacitance CINVIN= 0 V dc; f = 1.0 Mhz measured from pin t

36、o VSSsee 4.3.1c 01 4 20 pF Output capacitance COUTVOUT= 0 V dc; f = 1.0 Mhz measured from pin to VSSsee 4.3.1c 01 4 20 pF Clock pin capacitance CCLKVIN= 0 V dc; f = 1.0 Mhz measured from pin to VSSsee 4.3.1c 01 4 20 pF Clk/Vppcapacitance CVPPVOUT= 0 V dc; f = 1.0 Mhz measured from pin to VSSsee 4.3.

37、1c 01 4 50 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Elect

38、rical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC+125C VCC= 4.5 V dc to 5.5 V dc (unless otherwise specified) Device type Group A subgroups Limits Unit Min Max Input to non-registered output 4/ tPDCL= 50 pF (See figures 4 and 5) 01 9, 10, 11 55 ns Input to output enable

39、4/ tPZXCL= 50 pF (See figures 4 and 5) 01 9, 10, 11 55 ns Input to output disable 4/ 5/ tPXZCL= 50 pF (See figures 4 and 5) output change = 500 mV 01 9, 10, 11 55 ns Asynchronous output 4/ clear time tCLRCL= 50 pF (See figures 4 and 5) 01 9, 10, 11 60 ns Input setup time 4/ tSU(See figures 4 and 5)

40、01 9, 10, 11 45 ns Input hold time 4/ tH01 9, 10, 11 0 ns Clock high time 2/ tCH01 9, 10, 11 22.5 ns Clock low time 2/ tCL01 9, 10, 11 22.5 ns Clock to output delay tCO101 9, 10, 11 30 ns Minimum clock period (register output feedback to register input, 3/ 6/ internal path) tCNT01 9, 10, 11 65 ns Ma

41、ximum frequency (1/tSU) 4/ 7/ 8/ fMAX01 9, 10, 11 22.2 MHz Minimum clock period (tSU+ tCO1) tP201 9, 10, 11 75 ns Internal maximum frequency (1/tCNT) 3/ 9/ fCNT01 9, 10, 11 15.4 MHz Asynchronous input 2/ 4/ setup time tASU01 9, 10, 11 10 ns See footnotes at end of table. Provided by IHSNot for Resal

42、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86864 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -5

43、5C TC+125C VCC= 4.5 V dc to 5.5 V dc (unless otherwise specified) Device type Group A subgroups Limits Unit Min Max Asynchronous input 2/ 4/ tAH(See figures 4 and 5) 01 9, 10, 11 15 ns Asynchronous clock 2/ high time tACH01 9, 10, 11 22.5 ns Asynchronous clock 2/ low time tACL01 9, 10, 11 22.5 ns As

44、ynchronous clock to output delay 2/ 4/ tAC0101 9, 10, 11 65 ns Asynchronous minimum clock period (register output feedback to register input, internal path) 3/ 10/ tACNT01 9, 10, 11 65 ns Asynchronous internal maximum frequency (1/tACNT) 11/ fACNT01 9, 10, 11 15.4 MHz 1/ Screening and characterizati

45、on of ac delay parameters is typically conducted while operating at less than maximum frequency. 2/ May not be tested, but shall be guaranteed to the limits specified in table I. 3/ Specified with device programmed as a 16 bit counter and no output loading. 4/ All array-dependent delays are specifie

46、d for an XOR pattern. This pattern involves two product terms and two pure inputs with all other product terms in the macrocell held low by one EPROM pulldown. Other patterns may result in longer delays than those specified. Delays involving only one product term such as tPXZare specified for an “XOR-like“ pattern which involves one pure input switching at a time, and the sing