DLA SMD-5962-87002 REV E-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块 2KX8双门静态随机存取存储器 氧化物半导体 数字主体储存器微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED D Update boilerplate. Add device types 17 through 24. Add vendor CAGE 61772 as source of supply for device types 17 through 24. Add case outline T. Editorial changes throughout. 94-09-06 M. A. Frye E Boilerplate update, part of 5 year review. ksr 0

2、6-08-16 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV E E E E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison

3、 DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-05-04 MICROCIR

4、CUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-87002 SHEET 1 OF 28 DSCC FORM 2233 APR 97 5962-E583-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

5、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance

6、 with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87002 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function

7、as follows: Device type Generic number Circuit function Access time 01 7132SA 2K X 8 dual port static RAM, MASTER 45 ns 02 7132SA 2K X 8 dual port static RAM, MASTER 90 ns 03 7132SA 2K X 8 dual port static RAM, MASTER 70 ns 04 7132SA 2K X 8 dual port static RAM, MASTER 55 ns 05 7132LA 2K X 8 dual po

8、rt static RAM, MASTER 45 ns 06 7132LA 2K X 8 dual port static RAM, MASTER 90 ns 07 7132LA 2K X 8 dual port static RAM, MASTER 70 ns 08 7132LA 2K X 8 dual port static RAM, MASTER 55 ns 09 7142SA 2K X 8 dual port static RAM, SLAVE 45 ns 10 7142SA 2K X 8 dual port static RAM, SLAVE 90 ns 11 7142SA 2K X

9、 8 dual port static RAM, SLAVE 70 ns 12 7142SA 2K X 8 dual port static RAM, SLAVE 55 ns 13 7142LA 2K X 8 dual port static RAM, SLAVE 45 ns 14 7142LA 2K X 8 dual port static RAM, SLAVE 90 ns 15 7142LA 2K X 8 dual port static RAM, SLAVE 70 ns 16 7142LA 2K X 8 dual port static RAM, SLAVE 55 ns 17 7132S

10、A 2K X 8 dual port static RAM, MASTER 35 ns 18 7132LA 2K X 8 dual port static RAM, MASTER 35 ns 19 7132SA 2K X 8 dual port static RAM, MASTER 25 ns 20 7132LA 2K X 8 dual port static RAM, MASTER 25 ns 21 7142SA 2K X 8 dual port static RAM, SLAVE 35 ns 22 7142LA 2K X 8 dual port static RAM, SLAVE 35 n

11、s 23 7142SA 2K X 8 dual port static RAM, SLAVE 25 ns 24 7142LA 2K X 8 dual port static RAM, SLAVE 25 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CQCC1-N52 52 square leadless chip carri

12、er Y See figure 1 48 dual-in-line Z GDIP1-T48 or CDIP2-T48 48 dual-in-line U See figure 1 48 square leadless chip carrier T See figure 1 48 flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted

13、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. Voltage on any pin with respect to ground 1/ - -0.5 V to +7.0 V Storage temperature range

14、 - -65C to +150C Power dissipation (PD) - 1 W Lead temperature (soldering, 5 seconds) - +270C Maximum junction temperature (TJ) 2/ - +150C Thermal resistance, junction-to-case (JC): Cases X and Z - See MIL-STD-1835 Case Y - 23C/W 3/ Case U - 24C/W 3/ Case T - 20C/W 3/ Maximum dc output current- 50 m

15、A 1.4 Recommended operating conditions. Case operating temperature range (TC) - -55C to +125C Input low voltage (VIL) - -0.5 to +0.8 V dc 1/ Input high voltage (VIH) - +2.2 V to VCC+0.5 V dc 1/ Supply voltage (VCC) - +4.5 V to +5.5 V dc 1/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standa

16、rds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integra

17、ted Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-H

18、DBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In

19、 the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Unless otherwise specified, all voltag

20、es are referenced to VSS. 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 3/ When a thermal resistance value for this case outline is included in MIL-STD-1835, that value shall super

21、sede the value specified herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electric

22、al performance characteristics. Test Symbol Conditions Group A Device Limits Unit -55C VIH 1,2,3 21,23 ports inactive, TTL 01-04 65 mA level inputs 09-12 18,20, 60 22,24 05,07,08, 55 13,15,16 06,14 45 19,23 195 Standby current, one ISB2CERand CEL VIH 1,2,3 17,21 185 port active, TTL Active port outp

23、uts open 20,24 160 level inputs 18,22 150 01,03,04, 135 mA 09,11,12 02,10 125 05,07,08, 110 13,15,16 06,14 100 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPP

24、LY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C VCC-0.2 V 1,2,3 01-04, 30 mA both ports inactive, VIN VCC-0.2 V or 09-12, CMOS level inputs

25、VINVCC-0.2 V 1,2,3 17,21 175 one port active, VIN VCC-0.2 V or 20,24 150 CMOS level inputs VINVCC-0.2 V 1,2,3 05-08, 4000 A VIN VCC-0.2 V or 13-16, VINVCC-0.2 V 9,10,11 05-08, 0 ns retention time 1/ VIN VCC-0.2 V or 13-16, VINVCC-0.2 V 9,10,11 05-08, tAVAV ns time VIN VCC-0.2 V or 13-16, 2/ VIN5 ns

26、before right address. 3. RV5L = Right address valid 5 ns before left address. 4. Same = Left and right addresses match within 5 ns of each other. 5. LL5R = Left CE = Low 5 ns before right CE . 6. RL5L = Right CE = Low 5 ns before left CE . 7. LW5R = Left and right CE = Low within 5 ns of each other.

27、 FIGURE 3. Truth tables - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 18 DSCC FORM 2234 APR 97 NOTE: For de

28、vice types 01-08, 17-20: BUSY is open drain and requires pull-up resistor. For device types 09-16, 21-24: BUSY is input. Pin names Left port Right port Names CEL CER Chip enable R/ WL R/ WR Read/write enable OEL OER Output enable BUSYL BUSYR Busy flag A0L- A10L A0R- A10R Address I/O0L-I/O7L I/O0R-I/

29、O7R Data input/output VCC Power GND Ground FIGURE 4. Functional block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E S

30、HEET 19 DSCC FORM 2234 APR 97 16-bit master/slave dual-port memory system NOTE: No arbitration in 7142 (slave). BUSY -in inhibits write in 7142 (slave). FIGURE 4. Functional block diagram - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

31、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 20 DSCC FORM 2234 APR 97 FIGURE 5. Timing diagrams and test conditions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

32、NDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 21 DSCC FORM 2234 APR 97 FIGURE 5. Timing diagrams and test conditions - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

33、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 22 DSCC FORM 2234 APR 97 FIGURE 5. Timing diagrams and test conditions - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice

34、nse from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 23 DSCC FORM 2234 APR 97 FIGURE 5. Timing diagrams and test conditions - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

35、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 24 DSCC FORM 2234 APR 97 NOTES: 1. R/ W is high for read cycles. 2. Device is continuously enabled, CE = VIL. 3. Addresses valid prior to or coin

36、cident with CE transition low. 4. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 5. CEL= CER= VIL. 6. OE = VIL. 7. R/ W = VIHduring address transition. 8. To ensure that the earlier of the two ports wins. 9. Write

37、cycle parameters should be adhered to in order to ensure proper writing. 10. Device is continuously enabled for both ports. 11. OE at low for the reading port. 12. A write occurs during the overlap (tELWHor tWLWH) of a low CE and a low R/ W . 13. tEHOLis measured from the earlier of CE or R/ W going

38、 high to the end of the write cycle. 14. If OE is low during a R/ W controlled write cycle, the write pulse width must be the larger of tWLWHor (tWLQZ+ tDVWH) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDVWH. If OE is high during an R/ W controlled write c

39、ycle, this requirement does not apply and the write pulse can be as short as the specified tWLWH. 15. During this period, the I/O pins are in the output state and input signals must not be applied. FIGURE 5. Timing diagrams and test conditions - Continued. Provided by IHSNot for ResaleNo reproductio

40、n or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 25 DSCC FORM 2234 APR 97 Output load legend Row Devices/conditions CL RL R1 1 02-04, 06-08, 10-12, and 14-16; 100 pF

41、1250 775 for all ac parameters except as indicated in row 3 2 01, 05, 09, 13, and 17-24; for all 30 pF 1250 775 ac parameters except as indicated in row 3 3 All devices; for ac parameters 5 pF 1250 775 (tOHQZ, tOLQZ, tWLQZ, and tWHOX) only 4 01-08; BUSY 100 pF 270 Not used 5 17-20; BUSY 30 pF 270 No

42、t used AC test conditions Input pulse levels GND to 3.0 V Input rise and fall times 5 ns Input timing reference levels 1.5 V Output reference levels 1.5 V Output load See above FIGURE 5. Timing diagrams and test conditions - Continued. NOTES: 1. Includes jig and probe capacitance. 2. See output load legend.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87002 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 26 DSCC FORM 2234 APR 97 TABLE II. Electrical test requirem