DLA SMD-5962-87513 REV C-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 4K X 1 AND 1K X 4 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON《硅单块4K X1和1K X4静态随机存取存储器 互补金属氧化物半导体 数字主存储器微型电路.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device types 07 through 09. Update boilerplate. Editorial changes throughout. 95-12-07 M. A. Frye B Add device type 10. Editorial changes throughout. 96-08-09 Raymond Monnin C Boilerplate update, part of 5 year review. ksr 06-08-16 Raymond Mo

2、nnin REV SHET REV C SHET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS D

3、RAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-02-02 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4K X 1 AND 1K X 4 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE

4、 67268 5962-87513 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E584-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC

5、 FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87513 01 L A

6、 Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 4096 x 1 CMOS static RAM 25 ns 02 4096 x 1 CMOS static RAM 35 ns 03 4

7、096 x 1 CMOS static RAM 45 ns 04 1024 x 4 CMOS static RAM 25 ns 05 1024 x 4 CMOS static RAM 35 ns 06 1024 x 4 CMOS static RAM 45 ns 07 1024 x 4 CMOS static RAM 25 ns 08 1024 x 4 CMOS static RAM 35 ns 09 1024 x 4 CMOS static RAM 45 ns 10 1024 x 4 CMOS static RAM 35 ns 1.2.2 Case outline(s). The case

8、outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 or CDIP2-T18 18 dual-in-line X See figure 1 18 flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rating

9、s. Voltage on any pin relative to VSS.-2.0 V dc to +7.0 V dc Voltage applied to outputs: devices 01-06, 10 -1.0 V dc to VCC+ 0.5 V dc devices 07-09 -0.5 V dc to +7.0 V dc Storage temperature range-65C to +150C Maximum power dissipation (PD): devices 01-06 1.0 W devices 07-09 0.605 W device 10 .0.660

10、 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case V.See MIL-STD-1835 Case X.15C/W Junction temperature (TJ) +175C 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be l

11、isted in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating c

12、onditions. Supply voltage (VCC)4.5 V dc to 5.5 V dc Supply voltage (VSS) 0 V Input high voltage (VIH) 2.0 V dc to VCC+ 0.5 V dc Input low voltage (VIL): devices 01-06, 10 -1.0 V dc to 0.8 V dc devices 07-09 -3.0 V dc to 0.8 V dc Case operating temperature range (TC).-55C to +125C 2. APPLICABLE DOCUM

13、ENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFE

14、NSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List

15、 of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA

16、 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

17、3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified ma

18、nufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Manag

19、ement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify w

20、hen the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Ter

21、minal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I

22、 and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FO

23、RM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with t

24、he PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compl

25、iance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of complia

26、nce. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers produ

27、ct meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notificati

28、on of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available

29、onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior t

30、o quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activit

31、y upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, e

32、xcept interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additiona

33、l criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CINand COUTmeasurement) shall be measured only for the initial test and after process or design changes wh

34、ich may affect capacitance. Sample size is fifteen devices with no failures and all input and output terminals tested. d. Subgroups 7 and 8 shall include verification of the truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

35、IRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V SS= 0 V unless otherwise specified 1/ Group A subgr

36、oups Device type Min Max Unit 01-03 80 04-09 110 VCCpower supply current (average) 2/ ICC1tAVAV= tAVAV(minimum) 1, 2, 3 10 120 mA 01-06, 10 15 VCCpower supply current (standby, stable TTL input levels) 2/ ICC2CE VIH, all other inputs VILor VIH1, 2, 3 07-09 10 mA 01-06 6.0 VCCpower supply current (st

37、andby, stable CMOS input levels) 2/ ICC3CE (VCC- 0.2 V), all other inputs 0.2 V or (VCC- 0.2 V) 1, 2, 3 10 10 mA 01-06 10 VCCpower supply current (standby, cycling CMOS input levels) 2/ ICC4CE (VCC- 0.2 V),all other inputs 0.2 V or (VCC- 0.2 V) 1, 2, 3 10 20 mA 01-06 5.0 Input leakage current, any i

38、nput IILKVCC= 5.5 V, VIN= 0.0 V to 5.5 V 1, 2, 3 07-10 10 A 01-06, 10 10 Off state output leakage current IOLKVCC= 5.5 V, VIN= 0.0 V to 5.5 V 1, 2, 3 07-09 50 A Output high voltage VOHIOUT= -4.0 mA, VIH= 2.0 V 1, 2, 3 All 2.4 V IOUT= 12 mA, VIL= 0.8 V 1, 2, 3 01-03 0.4 Output low voltage VOLIOUT= 8.

39、0 mA, VIL= 0.8 V 1, 2, 3 04-10 0.4 V 01-06 4.0 Input capacitance CINVIN= 0.0 V to 3.0 V, f = 1.0 MHz, TA= +25C, See 4.3.1c 4 07-10 8.0 pF 01-06 4.0 Output capacitance COUTVIN= 0.0 V to 3.0 V, f = 1.0 MHz, TA= +25C, See 4.3.1c 4 07-10 8.0 pF Functional tests See 4.3.1d 7, 8A, 8B All 01,04, 07 25 02,0

40、5, 08,10 35 Chip enable access time tELQVSee figures 4 and 5 9, 10, 11 03,06,09 45 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUMBUS COLUMB

41、US, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Limits Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V SS= 0 V unless otherwise specified 1/ Group A subgroups Device type Min Max Unit 01,04,07 25 02,05,08,10 35 R

42、ead cycle time tAVAVSee figures 4 and 5 3/ 9, 10, 11 03,06,09 45 ns 01,04,07 25 02,05,08,10 35 Address access time tAVQVSee figures 4 and 5 4/ 9, 10, 11 03,06,09 45 ns 01-06, 09 5.0 10 3.0 Output hold after address change tAVQXSee figures 4 and 5 9, 10, 11 07,08 0 ns 01-06 5.0 07 8 08,09 10 Chip ena

43、ble to output active tELQXSee figures 4 and 5 5/ 9, 10, 11 10 2.0 ns 01,05, 06, 08-10 0 20 02,03 0 30 Chip disable to output inactive tEHQZSee figures 4 and 5 5/ 6/ 9, 10, 11 04,07 0 15 ns Chip enable to power up tELPUSee figures 4 and 5 5/ 9, 10, 11 All 0 ns Chip enable to power down tEHPDSee figur

44、es 4 and 5 5/ 9, 10, 11 All 30 ns 01-09 50 Input rise and fall times tT5/ 7/ 9, 10, 11 10 10 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87513 DEFENSE SUPPLY CENTER COLUM

45、BUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Limits Test Symbol Conditions -55C TC+125C VCC= 4.5 V to 5.5 V SS= 0 V unless otherwise specified 1/ Group A subgroups Device type Min Max Unit 01,04,07 25 02,05,

46、08,10 35 Write cycle time tAVAVSee figures 4 and 6 9, 10, 11 03,06,09 45 ns 01,04 15 02,07 20 03,05,10 25 08 30 Write pulse width tWLWHSee figures 4 and 6 9, 10, 11 06,09 35 ns 01,04,07 20 02,05,08,10 30 Chip enable to end of write tELEHSee figures 4 and 6 9, 10, 11 03,06,09 40 ns 01,05,06,10 15 02,

47、03,08,09 20 04 10 Data setup to end of write tDVWHSee figures 4 and 6 9, 10, 11 07 12 ns Data hold after end of write tWHDXSee figures 4 and 6 9, 10, 11 All 0 ns 01,04,07 20 02,05,08,10 30 09 35 Address setup to end of write tAVWHSee figures 4 and 6 9, 10, 11 03,06 40 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS