DLA SMD-5962-87515 REV C-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 8K X 8 UV EPROM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add six new device types for vendor CAGE number 65786. Add vendor CAGE number 1FN41 as a source of supply for devices 01KX, 02KX, 03KX, and 04KX. Change to vendor similar part number for vendor CAGE number 1FN41. Change to margin test method A for vendor CA

2、GE number 66579. Remove 4.5.1, 4.5.2, 4.5.3, figures 5 and 6, and table III from drawing. Change to parameters tCSand tDFin table I. Change to figures 2 and 3. Editorial changes throughout. 93-01-21 M. A. Frye B 5 year review and update. Changed input capacitance from 6 pF to 10 pF. ksr 06-06-06 Ray

3、mond Monnin C Sheet 8, FIGURE 3, Output Load Circuit values, change R1value for device types 11 and 12 from 250 ohms to 98 ohms, and VTHfrom 1.9 volts to 2.01 volts. Boilerplate updates as needed. glg 12-03-14 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SH

4、EET REV STATUS REV C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR US

5、E BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 8K X 8 UV EPROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-06-21 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-87515 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E518

6、-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requi

7、rements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962-87515 01 J A | | | | | | | | | | | | Drawing number Device type Case outline Le

8、ad finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 8K x 8 UV EPROM 45 ns 02 8K x 8 UV EPROM 55 ns 03 8K x 8 UV EPROM 70 ns 04 8K x 8 UV EPROM 90 ns 05 8K

9、x 8 UV EPROM 45 ns 06 8K x 8 UV EPROM 55 ns 07 8K x 8 UV EPROM 35 ns 08 8K x 8 UV EPROM 35 ns 09 8K x 8 UV EPROM 45 ns 10 8K x 8 UV EPROM 55 ns 11 8K x 8 UV EPROM 25 ns 12 8K x 8 UV EPROM 25 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline

10、 letter Descriptive designator Terminals Package style J GDIP1-T24 OR CDIP2-T24 24 Dual-in-line 2/ K GDFP2-F24 OR CDFP3-F24 24 Flat pack 2/ L GDIP3-T24 OR CDIP4-T24 24 Dual-in-line 2/ 3 CQCC1-N28 28 Square leadless chip carrier 2/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535,

11、appendix A. 1.3 Absolute maximum ratings. Storage temperature . -65C to +150C Voltages on any pin with respect to ground . -0.5 V dc to +7.0 V dc VPPwith respect to ground . -0.5 V dc to +14.0 V dc Maximum power dissipation (PD) 3/ . 1 W Lead temperature (soldering, 10 seconds) +300C Thermal resista

12、nce, junction-to-case (JC) MIL-STD-1835 Junction temperature (TJ) 4/ +150C 1.4 Recommended operating conditions. 1/ Case operating temperature (TC). -55C to +125C Supply voltage (VCC) +4.5 V dc to +5.5 V dc 1/ Generic numbers are listed on the Standardized Microcircuit Drawing Bulletin at the end of

13、 this document and will also be listed in MIL-HDBK-103. 2/ Lid shall be transparent to permit ultraviolet light erasure. 3/ Must withstand the added PDdue to short circuit test, e.g., IOS. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening con

14、ditions in accordance with method 5004 of MIL-STD-883.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. AP

15、PLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPA

16、RTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-H

17、DBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

18、2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENT

19、S 3.1 Item requirements The individual item requirements for device classes Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function

20、 as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as

21、specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Un

22、programmed or erased devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C inspection (see 4.3), the devices shall be programmed by the manufacturer prior to test in a checkerboard patte

23、rn or equivalent (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total numbers of bits programmed. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached

24、 altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requireme

25、nts shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43

26、218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions Group A Device Limits -55C TC+125C subgroups types Unit VSS= 0 V 4.5 V VCC 5.5 V unless otherwise specified Min Max Input leakage current ILIVIN= 5.5 V and GND 1,2,3 All 10

27、 A Output leakage current ILOVOUT= 5.5 V and GND 1,2,3 All 10 A 01-10 120 Operating supply ICC1CS = VIL, VCC= 5.5 V current (active) 1/ D0 to D7 = 0 mA 1,2,3 11-12 140 mA f = max 01-07 40 Standby current, ICC2CS = 2.0 V, VCC= 5.5 V 1,2,3 mA TTL inputs 12 50 01-07 40 Standby current, ICC3VCC= 5.5 V,

28、CS = VCC-0.3 V 1,2,3 mA CMOS inputs 12 50 Input low voltage VILVCC= 4.5 V and 5.5 V 1,2,3 All 0.8 V Input high voltage VIHVCC= 4.5 V and 5.5 V 1,2,3 All 2.0 V Output voltage low VOLVCC= 4.5 V, IOL= 16 mA 01-10 0.45 V VIH= 2.0 V, 1,2,3 VIL= 0.8 V IOL= 6 mA 11,12 0.4 Output voltage high VOHVCC= 4.5 V,

29、 IOH= -4 mA 01-10 VIH= 2.0 V, 1,2,3 2.4 V VIL= 0.8 V IOH= -2 mA 11,12 Output short circuit IOSVO= GND 1,2,3 All -100 mA current 2/ 3/ Input capacitance 3/ CINf = 1.0 MHz VIN= 0 V 10 TC= +25C 4 All pF See 4.3.1e VOUT= 0 V 12 Output capacitance 3/ COUTVCC= 5.5 V See footnotes at end of table. Provided

30、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test S

31、ymbol Conditions Group A Device Limits -55C TC+125C subgroups types Unit VSS= 0 V 4.5 V VCC 5.5 V unless otherwise specified Min Max 9,10,11 11,12 25 ns 07,08 35 Address to output tACCVCC= 4.5 V 01,05 delay See figures 3 and 4 09 45 02,06 10 55 03 70 04 90 9,10,11 11 15 ns 08 20 12 25 CS to output d

32、elay tCS 09 30 01,02 10 35 07 40 05 45 03,04, 55 06 11 15 08,12 25 CS high to output tDF 9,10,11 09 30 ns float 3/ 4/ 01,02 07,10 35 05 45 03,04, 55 06 Address to output hold tOH 9,10,11 All 0 ns 3/ 1/ TTL inputs: VIL 0.8 V, VIH 2.0 V. 2/ Not more than one output should be shorted at a time, and sho

33、rt circuit test (IOS) should not exceed 30 seconds. 3/ Tested initially and after any design or process changes which may affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 4/ Transition is measured at steady-state high level -500 mV or steady-state low leve

34、l +500 mV on the output from the 1.5 V level on the input with the output load in figure 3, circuit B. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

35、ISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Device types All Case outlines J, K, L 3 Terminal number Terminal symbol 1 A7NC 2 A6A73 A5A64 A4A55 A3A46 A2A37 A1A28 A0A19 O0A010 O1NC 11 O2O012 GND O113 O3O214 O4GND 15 O5NC 16 O6O317 O7O418 A12O519 A11O620 CS O721 A10NC 22 A9A1223 A8A1124 VCCCS 25 - A10

36、26 - A927 - A828 - VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Mode

37、VCCCS / VPPO0 O7Read 5 V 10% VILFF H Output disable 5 V 10% VIHHigh Z Program 1/ VCCVPPData in Verify 1/ VCCVILProgrammed byte 1/ See 4.5 herein. Device types 01 - 04 Type Mode Outputs A12A11CS A10A9A8VCCPower All Read DOUTA12A11VILA10A9A8VCCICC105-07, 12 Not selected High-Z A12A11VIHA10A9A8VCCICC2,

38、 ICC308-11 Not selected High-Z A12A11VIHA10A9A8VCCICC1All Program 1/ DINVILPVPPVILPLatch VILPVIHPVCCICC1All Program inhibit 1/ High-Z VILPVPPVILPLatch VIHPVIHPVCCICC1All Program verify 1/ DOUTVILPVPPVILPLatch VIHPVILPVCCICC1All Blank check 1/ DOUTVILPVPPVILPLatch VIHPVILPVCCICC11/ See 4.5 herein. De

39、vice types 05- 12 FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Device types All

40、R198 VTH2.01 V FIGURE 3. Output load circuits or equivalent circuit. FIGURE 4. AC read timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87515 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

41、ISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due

42、to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with

43、 a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPROMS. When specified,

44、 devices shall be erased in accordance with the procedures and characteristics specified in 4.4 herein. 3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 herein. 3.6.3 Verification of erasure of programmed EPROMS. When specified, devic