DLA SMD-5962-87520 REV D-2005 MICROCIRCUIT PROGRAMMABLE INTERVAL TIMER MONOLITHIC SILICON《硅单块 程序间隔计时器微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R055-93. - JT 92-12-21 Monica L. Poelking B Changes in accordance with NOR 5962-R021-99. LTG 00-10-05 Monica L. Poelking C Modify paragraphs 3.1 and 3.5.1 to allow product to be marked with “QD” certification m

2、ark. Update boilerplate. TVN 00-10-05 Monica L. Poelking D Update boilerplate to MIL-PRF-38535 requirements. CFS 05-09-07 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS SMD HAS BEEN REPLACED. REV SHEET REV D SHEET 15 REV D D D D D D D D D D D D D D REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11

3、 12 13 14 PMIC N/A PREPARED BY Ray Monnin CHECKED BY Da Di Cenzo DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck DRAWING APPROVAL DATE 87-06-22 MICROCIRCUIT, PROGRAMMABLE INTERVAL TIMER, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-87520 STAN

4、DARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL D SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E410-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A

5、 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-3

6、8535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87520 01 J X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Dev

7、ice type 1/ Generic number Circuit function 01 8253 Programmable interval timer 02 8253 Programmable interval timer 03 8253-5 Programmable interval timer 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Packa

8、ge style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range with respect to ground (any pin) -0.5 V dc to +7.0 V dc Maximum power dissi

9、pation (PD) 1.0 W Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds). +270C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ). +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) 5.0 V dc Minimum high level input v

10、oltage (VIH) . 2.2 V dc Minimum low level input voltage (VIL). -0.5 V dc Maximum high level input voltage (VIH) VCC+ 0.5 V dc Maximum low level input voltage (VIL) 0.7 V dc Case operating temperature range (TC) . -55C to +125C _ 1/ Device types 01 and 02 are equivalent. Provided by IHSNot for Resale

11、No reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.

12、 The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manuf

13、acturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard

14、Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a con

15、flict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item r

16、equirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transition

17、al certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements h

18、erein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modif

19、ied to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified i

20、n MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Block diagram.

21、The block diagram shall be as specified on figure 3. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figures 4 and 5. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall

22、apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted

23、 without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN list

24、ed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indic

25、ator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with

26、A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved sour

27、ce of supply in MIL-HDBK-103 (see 6.7 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conforman

28、ce. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review.

29、 DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted with

30、out license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwi

31、se specified Device type Group A subgroups Min Max Unit Input low voltage VILVCC= 5 V 10% All 1, 2, 3 0.7 V Input high voltage VIHVCC= 5 V 10% All 1, 2, 3 2.2 V Output low voltage VOLVCC= 5 V 10%, IOL= 1.6 mA All 1, 2, 3 0.45 V Output high voltage VOHVCC= 5 V 10%, IOH= -150 A All 1, 2, 3 2.4 V Input

32、 load current IILVCC= 5.5 V VIN= VCCto 0.0 V All 1, 2, 3 20 A Output float leakage IOFLVCC= 5.5 V VOUT= VCCto 0.0 V All 1, 2, 3 20 A VCCsupply current 1/ ICCVCC= 5.5 V Outputs unloaded static All 1, 2, 3 160 mA Input capacitance CIN fC = 1 MHz, TA = 25C VCC= GND = 0.0 V See 4.3.1d All 4 10 pF Input/

33、Output capacitance CI/O TA = 25C VCC= GND = 0.0 V Unmeasured pins returned to VSSSee 4.3.1d All 4 20 pF Functional test See 4.3.1c All 7, 8 01, 02 50 Address stable before RD tAR03 9, 10, 11 30 ns Address hold time for RD tRA All 9, 10, 11 5 ns 01, 02 400 RD pulse width 3/ tRR 03 9, 10, 11 300 ns 01

34、, 02 300 Data delay from RD 4/ tRD 03 9, 10, 11 200 ns 01, 02 25 125 RD to data floating 5/ tDF 03 9, 10, 11 25 100 ns Recovery time between RD and any other control signal 5/ tRV See figures 4 and 5 2/ All 9, 10, 11 1 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or

35、networking permitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions -55C TC

36、 +125C 4.5 V VCC 5.5 V unless otherwise specified Device type Group A subgroups Min Max Unit 01, 02 50 Address stable before WR tAW 03 9, 10, 11 30 ns Address hold time for WR tWA All 9, 10, 11 30 ns 01, 02 400 WR pulse width 3/ tWW 03 9, 10, 11 300 ns 01, 02 300 Data setup time for WR tDW03 9, 10,

37、11 250 ns 01, 02 40 Data hold time for WR tWD 03 9, 10, 11 30 ns Recovery time between WR and any other control signal 5/ tRV All 9, 10, 11 1 s Clock period tCLK All 9, 10, 11 380 DC 5/ ns High pulse width tPWH All 9, 10, 11 230 ns Low pulse width tPWL All 9, 10, 11 150 ns Gate width high tGW All 9,

38、 10, 11 150 ns Gate width low 5/ tGL All 9, 10, 11 100 ns Gate setup to CLK high tGS All 9, 10, 11 100 ns Gate hold after CLK high tGH All 9, 10, 11 55 ns Output delay from CLK low 4/ tOD All 9, 10, 11 400 ns Output delay from gate low 4/ tODG See figures 4 and 5 2/ All 9, 10, 11 300 ns 1/ ICCis mea

39、sured in a static condition with no output loads applied. 2/ Test conditions: VIL= 0.45 V, VIH= 2.4 V VOL= 0.8 V, VOH= 2.2 V 3/ If clock low occurs less than 100 ns after the rising edge of READ or WRITE, the counter selected during the READ or WRITE could be affected. 4/ Test condition: CL= 100 pF.

40、 5/ Guaranteed if not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type All Case

41、 outline J Terminal number Terminal symbol Terminal number Terminal symbol 1 D7 13 OUT1 2 D6 14 GATE1 3 D5 15 CLK1 4 D4 16 GATE2 5 D3 17 OUT2 6 D2 18 CLK2 7 D1 19 A0 8 D0 20 A1 9 CLK0 21 CS 10 OUT0 22 RD 11 GATE0 23 WR 12 GND 24 VCC FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo rep

42、roduction or networking permitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 CS RD WR A1 A0 0 1 0 0 0 Load counter number 0 0 1 0 0 1 Load counter number 1 0 1 0

43、1 0 Load counter number 2 0 1 0 1 1 Write mode word 0 0 1 0 0 Read counter number 0 0 0 1 0 1 Read counter number 1 0 0 1 1 0 Read counter number 2 0 0 1 1 1 No-operation three-state 1 X X X X Disable three-state 0 1 1 X X No-operation three-state Mode register for latching count A0, A1 = 11 D7 D6 D

44、5 D4 D3 D2 D1 D0 SC1 SC0 0 0 X X X X SC1, SC0 - Specify counter to be latched. D5, D4 - 00 designates counter latching operation. X Dont care. Control word format D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking p

45、ermitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Definition of control SC Select counter SC1 SC0 0 0 Select counter 0 0 1 Select counter 1 1 0 Select counter 2

46、 1 1 Illegal RL Read/Load RL1 RL0 0 0 Counter latching operation 1 0 Read/load most significant byte only 0 1 Read/load least significant byte only 1 1 Read/load least significant byte first, then most significant byte M - Mode M2 M1 M0 0 0 0 Mode 0 0 0 1 Mode 1 X 1 0 Mode 2 X 1 1 Mode 3 1 0 0 Mode

47、4 1 0 1 Mode 5 FIGURE 2. Truth tables - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87520 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 9

48、7 BCD 0 Binary counter 16-bits 1 Binary code decimal (BCD) counter (4 decades) Gate pin operations summary Signal status Modes Low or going low Rising High 0 Disables counting - Enables counting 1 - 1. Initiates counting 2. Resets output after next clock - 2 1. Disables counting 2. Sets output immediately high 1. Reloads counter 2. Initiates counting Enables counting 3 1. Disables counting 2. Sets output immediately high Initiates counting Enables counting 4 Disables counting - Enables counting 5 - Initiates c