DLA SMD-5962-87539 REV L-2010 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE ARRAY LOGIC MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Delete programming waveforms, 4.5.1, 4.5.2, and table III. Changes to 4.5 and 6.6. Editorial changes throughout. Redrawn. 90-06-25 M. Poelking D Change CINand COUTin table I, IAW NOR 5962-R003-9l. 91-09-20 M. A. Frye E Add device type 05; editori

2、al changes throughout. Redrawn. 93-02-02 M. A. Frye F Add device type 06; editorial changes throughout. Redrawn. 93-05-04 M. A. Frye G Changes in accordance with NOR 5962-R187-93 93-06-17 M. A. Frye H Changes in accordance with NOR 5962-R207-93 93-07-29 M. A. Frye J Update drawing to current require

3、ments. Editorial changes throughout. - gap 02-01-04 Raymond Monnin K Boilerplate update, part of 5 year review. ksr 08-04-25 Robert M. Heber L Corrected IILand IIHparameters in Table I. ksr 10-03-29 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV L SHET 15 R

4、EV STATUS REV L L L L L L L L L L L L L L OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DE

5、PARTMENTS APPROVED BY M. A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE, PROGRAMMABLE ARRAY LOGIC, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-10-20 AMSC N/A REVISION LEVEL L SIZE A CAGE CODE 67268 5962-87539 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962

6、-E254-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87539 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describe

7、s device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87539 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.

8、2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function tPD01 C22V10 22-input 10-output AND-OR-logic array 25 ns 02 C22V10 22-input 10-output AND-OR-logic array 30 ns 03 C22V10 22-input 10-output AND-OR

9、-logic array 40 ns 04 C22V10 22-input 10-output AND-OR-logic array 20 ns 05 C22V10 22-input 10-output AND-OR-logic array 15 ns 06 C22V10 22-input 10-output AND-OR-logic array 10 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive

10、 designator Terminals Package style K GDFP2-F24, CDFP3-F24 24 Flat package 1/ L GDIP3-T24, CDIP4-T24 24 Dual-in-line package 1/ 3 CQCC1-N28 28 Square chip carrier package 1/ X GQCC1-J28 28 “J“ lead chip carrier package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix

11、A. 1.3 Absolute maximum ratings. 2/ Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range -2.0 V dc to +7.0 V dc 3/ Output voltage applied range -0.5 V dc to +7.0 V dc 3/ Output sink current 16 mA Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximum power dissipation (PD) 4

12、/ . 1.2 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds maximum) +260C 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc to 5.5 V dc High level input voltage (VIH) . 2.0 V dc minimum Low level input voltage (VIL) 0.8 V dc maximum _ 1/ Lid shal

13、l be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to VSS. 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 4/ Mus

14、t withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87539 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 3 DSCC FORM

15、2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation

16、or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENS

17、E HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia,

18、 PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtaine

19、d. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified

20、 manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Ma

21、nagement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identif

22、y when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal conn

23、ections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When re

24、quired in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, or C (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells t

25、o any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified h

26、erein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87539 DEFENSE SUPP

27、LY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be

28、in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not ma

29、rking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-3

30、8535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to list

31、ing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of mi

32、crocircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. Defense Supply Center Columbus (DSCC), DSCCs agent, and the acquiring activity retain the option to review the

33、 manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configur

34、ations; two processing options are provided for selection in the contract. 3.10.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table II. It is recommended that users perform subgroups 7 and 9 after programming to verify th

35、e specific program configuration. 3.10.2 Manufacturer programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.11 Processing EPLDS. Al

36、l testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.11.2 Programmability of EPLDS. When spec

37、ified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.11.3 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.5 herein) to the specified pattern or erased (see 4.4 herei

38、n). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. Provided by IHSNot for ResaleNo repr

39、oduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87539 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ VSS= 0 V -5

40、5C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level output VOHIO= -2.0 mA 1, 2, 3 All 2.4 V voltage Low level output VOLIO= 12.0 mA 1, 2, 3 All 0.5 V voltage High impedance output IOZVO= GND and VO= 5.5 V 1, 2, 3 All -40 40 A leakage cur

41、rent 2/ VCC= 5.5 V High level input IIHVIH= 5.5 V 1, 2, 3 All -10 +10 A current Low level input current IILVIL= GND 1, 2, 3 All -10 +10 A Supply current ICCVCC= 5.5 V 1, 2, 3 01-05 100 mA 06 160 Output short circuit IOSVCC= 5.5 V 1, 2, 3 01-05 -30 -90 mA current 3/ 4/ VO= 0.5 V 06 -30 -120 Input cap

42、acitance CINVI= 0 V, VCC= 5.0 V 4 All 10 pF 4/ 5/ TA= +25C, f = 1 MHz See 4.3.1c Output capacitance COUTVO= 0 V, VCC= 5.0 V 4 All 10 pF 4/ 5/ TA= +25C, f = 1 MHz See 4.3.1c Functional testing See 4.3.1e 7, 8 All Input or feedback to tPDVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 25 ns non-registered output S

43、ee figure 4, circuit B and 02 30 figure 5 03 40 04 20 05 15 06 10 Clock to output tCO9, 10, 11 01, 04 15 ns 02 20 03 25 05 10 06 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596

44、2-87539 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ VSS= 0 V -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise spec

45、ified Min Max Input to output enable tEAVCC= 4.5 V, CL= 5 pF 9, 10, 11 01 25 ns See figure 4, circuit A 02 30 and figure 5 03 40 04 20 05 15 06 10 Input to output disable tER9, 10, 11 01 25 ns 02 30 03 40 04 20 05 15 06 10 Clock period tPVCC= 4.5 V, CL= 50 pF 9, 10, 11 01 33 ns See figure 4, circuit

46、 B, 02 40 and figure 5 03 55 04 32 05 20 06 7 Clock pulse width tW9, 10, 11 01, 04 15 ns 4/ 6/ 02 20 03 27 05 6 06 3.5 Setup time 4/ 6/ tS9, 10, 11 01 18 ns 02 20 03 30 04 17 05 10 06 5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

47、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87539 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ VSS= 0 V -55C TC+125C 4.5 V VCC 5.5 V Group A

48、subgroups Device type Limits Unit unless otherwise specified Min Max Hold time 4/ 6/ tHVCC= 4.5 V, CL= 50 pF See figure 4, circuit B, 9, 10, 11 All 0 ns Maximum clock fMAXand figure 5 9, 10, 11 01 30 MHz frequency 4/ 6/ 02 25 1/(tCO+ tS) 03 18 04 31 05 50 06 77 Asynchronous reset tAW9, 10, 11 01 25 ns pulse width 02 30 03 40 04 20 05 15 06 7 Asynchronous reset tAR9, 10, 11 01 25 ns recovery time 02 30 03 40 04