DLA SMD-5962-87548 REV D-2005 MICROCIRCUIT DIGITAL PROGRAMMABLE COMMUNICATION INTERFACE MONOLITHIC SILICON《硅单块 可编程交流界面数字微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R020-99. - LTG 99-01-28 Monica L. Poelking B Changes in accordance with NOR 5962-R009-00. - TVN 00-01-12 Monica L. Poelking C Correct test conditions VINand VOUTfor IILand IOFL, respectively, in table I. Delete

2、 IOHand IOLin footnote 3/ in table I. Add test circuit and output waveform for data floating test (tDF). Update boilerplate. Editorial changes throughout. - TVN 00-07-14 Monica L. Poelking D Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-09-07 Thomas M. Hess THE ORIGINAL FIRST SHEET OF T

3、HIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 REV D D D D D D D D D D D D D D REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Ray Monnin CHECKED BY D. A. DiCenzo DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-399

4、0 http:/www.dscc.dla.mil APPROVED BY N. A. Hauck DRAWING APPROVAL DATE 87-08-26 MICROCIRCUIT, DIGITAL, PROGRAMMABLE COMMUNICATION INTERFACE, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-87548 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEP

5、ARTMENT OF DEFENSE AMSC N/A REVISION LEVEL D SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E411-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REV

6、ISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following

7、example: 5962-87548 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 8251A Programmable communication interface 02 8251A Progra

8、mmable communication interface 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead f

9、inish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7 V dc Input voltage range -0.5 V dc to +7 V dc VCCwith respect to VSS. -0.5 V dc to +7 V dc All signal voltages with respect to VSS-0.5 V dc to +7 V dc Maximum power dissipation (PD)

10、 1.0 W Storage temperature range -65C to +150C Lead temperature (soldering, 5 seconds). +270C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ). +150C 1.4 Recommended operating conditions. Supply voltage range (VCC): Device type 01 +4.5 V dc to +5.5 V dc Device t

11、ype 02 +4.75 V dc to +5.25 V dc Minimum low level input voltage (VIL). -0.5 V dc Minimum high level input voltage (VIH) . +2.2 V dc Maximum low level input voltage (VIL) +0.8 V dc Maximum high level input voltage (VIH) VCCCase operating temperature range (TC) . -55C to +125C Provided by IHSNot for R

12、esaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handb

13、ooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits,

14、Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Stan

15、dard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of

16、a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual i

17、tem requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted trans

18、itional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requireme

19、nts herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been

20、modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specif

21、ied in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 True table. The true table shall be as speciified on figure 2. 3.2.4 Block diagr

22、am. The block diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics a

23、re as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo

24、 reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The p

25、art shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certificatio

26、n/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used.

27、For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in o

28、rder to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements

29、 herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this

30、drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo repr

31、oduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC

32、 +125C VCC= 5 V 10% for device type 01 VCC= 5 V 5% for device type 02 unless otherwise specified Device type Group A subgroups Min Max Unit Input low voltage VILAll 1, 2, 3 0.8 V Input high voltage VIHAll 1, 2, 3 2.2 V Low level output voltage VOLIOL= 2.2 mA All 1, 2, 3 0.45 V High level output volt

33、age VOHIOH= -400 A All 1, 2, 3 2.4 V Input leakage current IILVIN= VCCmax and 0.45 V All 1, 2, 3 10 1/ A Output float leakage current IOFLVOUT= VCCmax and 0.45 V All 1, 2, 3 10 1/ A Power supply current ICCOutputs unloaded static 2/ All 1, 2, 3 120 mA Input capacitance CINfC= 1 MHz See 4.3.1d 4 10 I

34、/O capacitance CI/O Unmeasured pins returned to GND See 4.3.1d All 4 20 pF Functional test See 4.3.1c All 7, 8 READ CYCLE Address stable before RD tARSee figure 4 3/ 4/ 5/ All 9, 10, 11 0 ns Address hold time to RD tRASee figure 4 3/ 4/ 5/ All 9, 10, 11 0 ns RD pulse width tRRSee figure 4 3/ 4/ All

35、9, 10, 11 250 ns Data delay from RD tRDSee figure 4 3/ 4/ 6/ 7/ All 9, 10, 11 200 ns RD to data floating tDFSee figure 4 3/ 4/ All 9, 10, 11 10 1/ 250 ns WRITE CYCLE Address stable before WR tAWSee figure 4 3/ 4/ All 9, 10, 11 0 ns Address hold time to WR tWASee figure 4 3/ 4/ All 9, 10, 11 20 ns WR

36、 pulse width tWWSee figure 4 3/ 4/ All 9, 10, 11 250 ns Data setup for WR tDWSee figure 4 3/ 4/ All 9, 10, 11 150 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENS

37、E SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions -55C TC +125C VCC= 5 V 10% for device type 01 VCC= 5 V 5% for device type 02 unless otherwise specified Device

38、type Group A subgroups Min Max Unit WRITE CYCLE - Continued Data hold for WR tWDSee figure 4 3/ 4/ All 9, 10, 11 20 ns Recover time between WR tRVSee figure 4 3/ 4/ 8/ All 9, 10, 11 6 1/ tCY OTHER TIMINGS Clock period 9/ tCY See figure 4 3/ 4/ 10/ 11/ All 9, 10, 11 320 1350 ns Clock high pulse width

39、 tHO See figure 4 3/ 4/ All 9, 10, 11 140 tCY 90 12/ ns Clock low pulse width tLO See figure 4 3/ 4/ All 9, 10, 11 90 ns TxD delay from falling edge of TxC tDTX See figure 4 3/ 4/ All 9, 10, 11 1 s 1 x Baud rate 1/ dc 64 16 x Baud rate 1/ dc 310 Transmitter input clock frequency fTX 64 x Baud rate 3

40、/ 4/ All 9, 10, 11 1/ dc 615 kHz 1 x Baud rate 12 16 x Baud rate 1 Transmitter input clock pulse width tTPW 64 x Baud rate See figure 4 3/ 4/ All 9, 10, 11 1 tCY 1 x Baud rate 15 16 x Baud rate 3 Transmitter input clock pulse delay tTPD 64 x Baud rate See figure 4 3/ 4/ All 9, 10, 11 3 tCY 1 x Baud

41、rate 1/ dc 64 16 x Baud rate 1/ dc 310 Receiver input clock frequency fRX 64 x Baud rate 3/ 4/ All 9, 10, 11 1/ dc 615 kHz 1 x Baud rate 12 16 x Baud rate 1 Receiver input clock pulse width tRPW 64 x Baud rate See figure 4 3/ 4/ All 9, 10, 11 1 tCY See footnotes at end of table. Provided by IHSNot f

42、or ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-87548 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Te

43、st Symbol Conditions -55C TC +125C VCC= 5 V 10% for device type 01 VCC= 5 V 5% for device type 02 unless otherwise specified Device type Group A subgroups Min Max Unit OTHER TIMINGS - Continued 1 x Baud rate 15 16 x Baud rate 3 Receiver input clock pulse delay tRPD 64 x Baud rate See figure 4 3/ 4/

44、All 9, 10, 11 3 tCY 01 12 TxRDY delay from center of last bit tTxRDYSee figure 4 3/ 4/ 13/ 02 9, 10, 11 14 tCY TxRDY fall from leading edge of WR tTxRDY CLEAR3/ 4/ 13/ All 9, 10, 11 400 nsRxRDY delay from center of last bit tRxRDY See figure 4 3/ 4/ 13/ All 9, 10, 11 26 tCY RxRDY fall from leading e

45、dge of WR tRxRDY CLEAR3/ 4/ 13/ All 9, 10, 11 400 nsInternal SYNDET delay from rising edge of RxC tIS See figure 4 3/ 4/ 13/ All 9, 10, 11 26 tCY External SYNDET setup after rising edge of RxC tES See figure 4 3/ 4/ 13/ All 9, 10, 11 16 tCY TxEMPTY delay from center of last bit tTXEMPTY See figure 4

46、 3/ 4/ 13/ All 9, 10, 11 20 tCY Control delay from rising edge of WR tWC See figure 4 3/ 4/ 13/ All 9, 10, 11 8 tCY Control to RD setup time tCR3/ 4/ 13/ All 9, 10, 11 20 tCY 1/ Guaranteed if not tested. 2/ ICCis measured in a static condition with outputs in the worst condition with all outputs unl

47、oaded. 3/ Test conditions: VCC= 5 V 10% for device type 01. VCC= 5 V 5% for device type 02. (See figure 4) VIL= 0.45 V VIH= 2.4 V VOL= 0.8 V VOH= 2.0 V 4/ Clock rise and fall times are controlled by the test equipment. Measurement of typical generated signal are tR= tF= 5 ns. 5/ Chip Select ( CS ) a

48、nd Command/Data (C/ D ) are considered as addresses. 6/ Test condition: CL= 100 pF (see figure 4). 7/ Assumes that address is valid before RD . 8/ This recovery time is for after a mode instruction only. Write data is allowed only when TxRDY = 1. Recovery time between writes for asynchronous mode is 8 tCYand for synchronous mode is 16 tCY. 9/ Due to test equipment limitations, actual tested values may differ from those specified but specified values are guaranteed. 10/ The TxC and RxC frequencies have the following limitations with respect to CLK: For 1 x B