ImageVerifierCode 换一换
格式:PDF , 页数:14 ,大小:109.11KB ,
资源ID:699050      下载积分:10000 积分
快捷下载
登录下载
邮箱/手机:
温馨提示:
如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
如填写123,账号就是123,密码也是123。
特别说明:
请自助下载,系统不会自动发送文件的哦; 如果您已付费,想二次下载,请登录后访问:我的下载记录
支付方式: 支付宝扫码支付 微信扫码支付   
注意:如需开发票,请勿充值!
验证码:   换一换

加入VIP,免费下载
 

温馨提示:由于个人手机设置不同,如果发现不能下载,请复制以下地址【http://www.mydoc123.com/d-699050.html】到电脑端继续下载(重复下载不扣费)。

已注册用户请登录:
账号:
密码:
验证码:   换一换
  忘记密码?
三方登录: 微信登录  

下载须知

1: 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。
2: 试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。
3: 文件的所有权益归上传用户所有。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 本站仅提供交流平台,并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

版权提示 | 免责声明

本文(DLA SMD-5962-87627 REV D-2009 MICROCIRCUIT DIGITAL FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf)为本站会员(amazingpat195)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-87627 REV D-2009 MICROCIRCUIT DIGITAL FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline S (flat package) for vendor CAGE 61772. Add the A version generic part. Changes to table I. Editorial changes throughout. 91-04-28 M. A. Frye B Add vendor CAGE 27014 and 75569. Technical changes in 1.4 and table I. Editorial chan

2、ges throughout. 91-11-25 M. A. Frye C Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. - LTG 06-07-06 Thomas M. Hess D Correct test condition for total supply current (ICCT) and add footnote 5/ in table I. Update boilerplate paragraphs as specified in current requireme

3、nts of MIL-PRF-38535. MAA. 09-12-23 Thomas M. Hess REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Jeffery Tunstall DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-39

4、90 http:/www.dscc.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, FAST CMOS, OCTAL D FLIP-FLOP WITH CLOCK ENABLE, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-05-23 AMSC N

5、/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-87627 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E127-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218

6、-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the f

7、ollowing example: 5962-87627 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54FCT377 Octal D flip-flop with clock enable, TTL

8、 compatible inputs 02 54FCT377A Octal D flip-flop with clock enable, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line package S GDF

9、P2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFEN

10、SE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc 2/ DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc

11、 2/ DC input diode current (IIK) . -20 mA DC output diode current (IOK) . -50 mA DC output current (IOUT) . 100 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 3/ Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . Se

12、e MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) 0.8 V dc Minimum high level input voltage (VIH) . 2.0 V dc Case operating temperature range (TC) . -55C to +125C Minimum setu

13、p time, Dn to CP (ts1): Device type 01 4.0 ns Device type 02 2.0 ns Minimum hold time, Dn to CP (th1): Device type 01 2.5 ns Device type 02 1.5 ns Minimum setup time, CEnullnullnullnullto CP (ts2): Device type 01 4.5 ns Device type 02 3.5 ns Minimum hold time, CEnullnullnullnullto CP (th2): Device t

14、ype 01 2.0 ns Device type 02 1.5 ns Minimum CP pulse width, high and low (tw): Device type 01 7.0 ns Device type 02 7.0 ns 1/ Unless otherwise specified, all voltages are referenced to ground. 2/ For VCC 6.5 V dc, the upper bound is limited to VCC. 3/ Must withstand the added PDdue to short circuit

15、test, e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Gover

16、nment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICAT

17、ION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard M

18、icrocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In

19、the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The

20、 individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been

21、granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to

22、the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Desig

23、n, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as

24、 specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. Provided by

25、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise s

26、pecified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgr

27、oup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to

28、space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a

29、“Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The

30、certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL

31、-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity reta

32、in the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW

33、ING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C VCC= 5.0 V dc 10% unless otherwise specified Group A subgroups Device type Limits Unit Mi

34、n Max High level output voltage VOHVCC= 4.5 V VIL= 0.8 V VIH= 2.0 V IOH= -300 A 1, 2, 3 All 4.3 V IOH= -12 mA 2.4 Low level output voltage VOLVCC= 4.5 V VIL= 0.8 V VIH= 2.0 V IOL= +300 A 1, 2, 3 All 0.2 V IOL= +32 mA 0.5 Input clamp voltage VIKVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.2 V High level in

35、put current IIHVCC= 5.5 V, VIN= 5.5 V 1, 2, 3 All 5.0 A Low level input current IILVCC= 5.5 V, VIN= GND 1, 2, 3 All -5.0 A Short circuit output current IOS 1/ VCC= 5.5 V, VOUT= GND 1, 2, 3 All -60 mA Quiescent power supply current (CMOS inputs) ICCQVIN 0.2 V or VIN 5.3 V VCC= 5.5 V, fI= 0.0 MHz 1, 2

36、, 3 All 1.5 mA Quiescent power supply current (TTL inputs) ICC 2/ VCC= 5.5 V, VIN= 3.4 V 1, 2, 3 All 2.0 mA Dynamic power supply current ICCD 3/ VCC= 5.5 V, CEnullnullnullnull= GND VIN 0.2 V or VIN 5.3 V One bit toggling, 50% duty cycle Outputs open 1, 2, 3 All 0.4 mA/ MHz Total power supply current

37、 ICC 4/ 5/ VCC= 5.5 V fCP= 10 MHz 50% duty cycle Outputs open One bit toggling at fI= 5 MHz 50% duty cycle CEnullnullnullnull= GND VIN 0.2 V or VIN 5.3 V 1, 2, 3 All 5.5 mA VCC= 5.5 V fCP= 10 MHz 50% duty cycle Outputs open Eight bits toggling at fI= 2.5 MHz 50% duty cycle CEnullnullnullnull= GND VI

38、N 3.4 V or VIN= GND 1, 2, 3 All 6.0 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DS

39、CC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC+125C VCC= 5.0 V dc 10% unless otherwise specified Group A subgroups Device type Limits Unit Min Max Input capacitance CINSee 4.3.1c 4 All 10 pF Output capacitance COUTSee 4.3.1c 4 All 12 pF

40、Functional tests See 4.3.1d 7, 8 All Propagation delay time, CP to On 6/ tPLH, tPHL CL= 50 pF minimum RL= 500 See figure 4 9, 10, 11 01 2.0 15.0 ns 02 2.0 8.3 1/ Not more than one output should be shorted at one time, and the duration of the short circuit condition should not exceed one second. 2/ T

41、TL driven input (VIN= 3.4 V); all other inputs at VCCor GND. 3/ This parameter is not directly testable, but is derived for use in total power supply calculations. 4/ ICC= ICCQ+ (ICCx DHx NT) + (ICCD(fCP/2 + fIx NI) Where: DH= Duty cycle for TTL inputs high. NT= Number of TTL inputs at DH. fI= Input

42、 frequency in MHz. NI= Number of inputs at fI. fCP= Clock frequency in MHz. 5/ For total current supply (ICCT) test in an ATE environment, the effect of parasitic output capacitive loading from the test environment must be taken into account, as its effect is not intended to be included in the test

43、results. The impact must be characterized and appropriate offset factors must be applied to the test result. 6/ The minimum limits are guaranteed, if not tested, to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN

44、DARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device types 01 and 02 Case outlines R, S, and 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CEnullnullnullnullO0

45、D0D1O1O2D2D3O3GND CP O4D4D5O5O6D6D7O7VCCFIGURE 1. Terminal connections. Device types 01 and 02 Operating mode Inputs Outputs CP CEnullnullnullnullDn On Load “1” l h H Load “0” l l L Hold (do nothing) h X No change X H X No change H = High voltage level h = High voltage level one setup time prior to

46、the low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition X = Irrelevant = Low-to-high clock transition FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

47、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR

48、AWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87627 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1