DLA SMD-5962-87649 REV A-2010 MICROCIRCUITS MEMORY DIGITAL NMOS 32K X 8 EEPROM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate as part of 5-year review. - glg 10-05-20 Charles Saffle THE ORIGINAL FIRST PAGE OF THE DRAWING HAS BEEN REPLACED. REV SHEET REV A A A SHEET 15 16 17 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9

2、10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 STANDARD MICROCIRCUIT CHECKED BY Charles Reusing http:/www.dscc.dla.mil DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUITS, MEMORY, DIGITAL, N

3、MOS, 32K X 8 EEPROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 19-JANUARY-1988 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-87649 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E241-10 Provided by IHSNot for ResaleNo reproduction or networking permitted wi

4、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcirc

5、uits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962-87649 01 X X Drawing number Device type Case outline Lead finish per (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s)

6、 shall identify the circuit function as follows: Generic Access Device type number 1/ Circuit function time 01 (8K X 8 EEPROM) 350 ns 02 (8K X 8 EEPROM) 300 ns 03 (8K X 8 EEPROM) 250 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: 1.2.3 Lead finis

7、h. The lead finish is as specified in MIL-PRF-38535, appendix A. Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line Y CQCC1-N32 32 Rectangular leadless chip carrier Z See figure 1 28 Flat pack 1.3 Absolute maximum ratings. 2/ Temperature under bias

8、 . -65C to +135C Storage temperature range. -65C to +150C Voltage on any pin with respect to ground . -1.0 V dc to +7.0 V dc DC output current . 5 mA Thermal resistance, junction-to-case (JC): Cases X and Y See MIL-STD-1835 Case Z . 15C/W Lead temperature (soldering, 10 seconds) . +300C Input voltag

9、e range -0.3 V dc to +6.5 V dc Endurance (minimum) . 10,000 cycles Data retention (minimum) . 10 years 1.4 Recommended operating conditions. Operating supply voltage 5.0 V dc +10% Case operating temperature range (TC) -55C to +125C High level input voltage +2.0 V dc to VCC+1.0 V dc Low level input v

10、oltage . -0.1 V dc to +0.8 V dc _ 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ Unless otherwise specified, all voltages are referenced to ground. Provided by IHSNot for ResaleNo rep

11、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The f

12、ollowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturi

13、ng, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microc

14、ircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this draw

15、ing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance

16、with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 m

17、ay be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall no

18、t affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design,

19、 construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth table. The truth table shall be as specified on figure 3. 3.2.3 Block diagram. The block diagram s

20、hall be as specified on figure 4. 3.2.4 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full c

21、ase operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shal

22、l be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. Provided by IHSNot for Res

23、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions Grou

24、p A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Supply current ICCCE = OE = VIL, 1,2,3 All 120 mA All I/Os are open, all other inputs at VCC Supply current ISBCE = VIH, OE = VIL, 1,2,3 All 60 mA (standby) all other inputs at VCC Input l

25、eakage current IILVIN= 0.0 V to 5.5 V 1,2,3 All 10 A Output leakage current IOL CE = OE = VIH, 1,2,3 All 10 A 1/ VOUT= 0.0 V to 5.5 V Low level input voltage VIL 1,2,3 All -0.1 0.8 V High level input voltage VIH 1,2,3 All 2.0 VCC+1.0 V Low level output VOLIOL= 2.1 mA, VCC= 4.5 V 1,2,3 All 0.4 V volt

26、age High level output VOHIOH= -400 A, VCC= 4.5 V 1,2,3 All 2.4 V voltage Input CIVIN= 0.0 V, VCC= 5.0 V 4 All 6 pF capacitance 2/ 3/ TA= +25C, f = 1 MHz See 4.3.1c Output COVIN= 0.0 V, VCC= 5.0 V 4 All 10 pF capacitance 2/ 3/ TA= +25C, f = 1 MHz See 4.3.1c Read cycle time tAVAVSee figure 5 9,10,11 0

27、1 350 ns 4/ 02 300 03 250 Address access time tAVAQ See figure 5 9,10,11 01 350 ns 4/ CE = OE = VIL 02 300 03 250 Chip enable access tELQV See figure 5 9,10,11 01 350 ns time 4/ OE = VIL 02 300 03 250 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted

28、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC

29、+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Output enable tOLQV See figure 5 9,10,11 All 100 ns access time CE = VIL Chip enable to output tELQX See figure 5 9,10,11 All 0 ns In low Z 2/ Chip disable to output tEHQZ 9,10,11 All 0 80 ns in high Z 2/ 5/ Output ena

30、ble to tOLQX 9,10,11 All 0 ns output in low Z 2/ Output disable tOHQZ 9,10,11 All 0 80 ns to output in high Z 2/ 5/ Output hold from tAXQX See figure 5 9,10,11 All 0 ns address change CE = OE = VIL Write cycle time tWLWL 9,10,11 All 10 ms WE controlled write 6/ See figures 6 and 7 Write cycle time t

31、ELEL 9,10,11 All 10 ms CE controlled write 6/ Address to WE setup tAVWL 9,10,11 All 0 ns time Address to CE setup tAVEL 9,10,11 All 0 ns time Address hold time tWLAX 9,10,11 All 150 ns after WE low Address hold time tELAX 9,10,11 All 150 ns after CE low CE to WE setup time tELWL 9,10,11 All 0 ns WE

32、to CE setup time tWLEL 9,10,11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 D

33、SCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC+125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max CE hold after WE high tWHEH See figures 6 and 7 9,10,11 All 0 ns WE hold after

34、CE high tEHWH 9,10,11 All 0 ns CE pulse width tELEH 9,10,11 All 150 ns WE pulse width tWLWH 9,10,11 All 150 ns OE high setup time tOHELSee figure 6, 7, 8, and 9 9,10,11 All 10 ns tOHWL7/ OE high hold time tWHOL 9,10,11 All 10 ns tEHOL7/ Write control tWHWL See figures 6 and 7 9,10,11 All 1 s recover

35、y time Data valid time tWLDV8/ See figure 6 9,10,11 All 300 ns Data setup time tDVEH 9,10,11 All 100 ns tDVWH Data hold time tEHDX 9,10,11 All 15 ns tWHDX Byte load cycle tWBLCSee figure 7 9,10,11 All 2 100 s Data valid to next write tDVWLSee figures 8 and 9 9,10,11 All 10 s CE to WE setup time tELW

36、LSee figure 10 9,10,11 All 10 ns Data to WE setup time tDVWL 9,10,11 All 10 ns 7/ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87649 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

37、OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55C TC+125C Group A Device Unit VSS= 0 V, 4.5 V VCC 5.5 V subgroups type unless otherwise specified Min Max Data hold after WE tWHDX See figure 1

38、0 9,10,11 All 50 ns high Write enable pulse tWLWH 9,10,11 All 175 ns width WE high to CE hold tWHEH 9,10,11 All 50 ns time VOEto WE setup time tOHWL 9,10,11 All 10 ns 7/ VOEhold time tWHOL 9,10,11 All 10 ns Erase cycle time tWLWL 9,10,11 All 10 ms 9/ 1/ Connect all address inputs and OE to VIHand me

39、asure IOLwith the output under test connected to VOUT. 2/ Tested initially and after any design changes that affect that parameter guaranteed to the limits specified in table I. 3/ All pins not being tested are to be open. 4/ Output load: 1 TTL gate and CL= 100 pF. Input rise and fall times 10 ns Input pulse levels: VIL= 0.0 V, VIH= 3.0 V Timing measurements reference level: Inputs: 1.5 V Outputs: 1.5 V 5/ Tested by inference only, but guaranteed to the limits of table I. 6/ tWLWLand tELELfor the byte write operations, define the time of the internal programming cycle