DLA SMD-5962-87700 REV B-2003 MICROCIRCUIT CMOS 8-BIT MULTIPLYING DIGITAL TO ANALOG CONVERTER MONOLITHIC SILICON《硅单块 8比特倍增数字到模拟转换器 互补金属氧化物半导体 数字微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor, CAGE 01295 for devices 01EX and 012X. Update format. Editorial changes throughout. 90-04-09 M. A. Frye B Update drawing to current requirements. drw 03-09-30 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. RE

2、V SHET REV SHET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Gary Zahn DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY

3、ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, CMOS, 8-BIT MULTIPLYING DIGITAL TO ANALOG CONVERTER, MONOLITHIC AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-12-14 SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-87700 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5

4、962-E555-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVI

5、SION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following e

6、xample: 5962-87700 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 7524 CMOS 8-bit multiplying buffered DAC with .5 LSB 02 7524

7、 CMOS 8-bit multiplying buffered DAC with .25 LSB 03 7524 CMOS 8-bit multiplying buffered DAC with .125 LSB 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 and CDIP2-T16 16 Dual-in-line

8、 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VDDto GND -0.3 V, +17 V VRFBto GND. 25 V Digital input voltage to GND. -0.3 V to VDDVREFto GND. 25 V VOUT1, VOUT2, 0 to GND -0.3 V to VDDPower d

9、issipation (PD): Up to +75C . 450 mW Derates above +75C. 6mW/C Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA). 120C/W 1.4 Recommended operating conditions.

10、Ambient operating temperature range (TA) . -55C to +125C Supply voltage range (VDD) +5 V to +15 V Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000

11、 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents

12、are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFE

13、NSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the

14、 specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this d

15、rawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level

16、B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the m

17、anufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These mo

18、difications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as spec

19、ified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Mode selection table. The mode selection table shall be as specified on figure

20、 2. 3.2.4 Write cycle timing diagram. The write cycle timing diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operatin

21、g temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performan

22、ce characteristics. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Resolution RES VDD= +5 V 1, 2, 3 All 8 Bits VDD= +15 V 8 Relative accuracy RA VDD= +5 V 1, 2, 3 All .5 LSB VDD= +15 V 1, 2, 3 01 .5 1 02 .5 2, 3 .25 VDD= +15 V, TA

23、= +25C 2/ 12 .25 VDD= +15 V 1 03 .5 2, 3 .125 VDD= +15 V, TA= +25C 2/ 12 .125 Gain error 3/ AEVDD= +5 V 1 All 1.0 %FSR 2, 3 1.4 VDD= +15 V 1 0.5 2, 3 0.6 Power supply rejection PSRR VDD= 10% VDD= +5 V 1 All .08 %/% 2, 3 .16 VDD= +15 V 1 .02 2, 3 .04 Output leakage current IOUT1IOLDB0-DB7 = 0 V, VDD=

24、 +5 V 1 All 50 nA WR = CS = 0 V 2, 3 400 VDD= +15 V 1 50 2, 3 200 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000

25、REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Output leakage current IOUT2IOLDB0-DB7 = VDD, VDD= +5 V 1 All 50 nA WR = CS

26、 = 0 V 2, 3 400 VDD= +15 V 1 50 2, 3 200 Input resistance (VREFpin) RINVDD= +5 V 1, 2, 3 All 5 20 k VDD= +15 V 5 20 Digital input high voltage VIHVDD= +5 V 1, 2, 3 All 2.4 V VDD= +15 V 13.5 Digital input low voltage VILVDD= +5 V 1, 2, 3 All 0.8 V VDD= +15 V 1.5 Digital input leakage current IINVIN=

27、0 V or VDDVDD= +5 V 1 All 1 A 2, 3 10 VDD= +15 V 1 All 1 2, 3 10 Supply current IDDAll digital inputs = VILor VIHVDD= +5 V 1, 2, 3 All 2 mA VDD= +15 V 2 All digital inputs = 0 V or VDDVDD= +5 V 1 All 100 A 2, 3 500 VDD= +15 V 1 All 100 2, 3 500 Gain temperature coefficient TCAE4/ VDD= +5 V 1, 2, 3 A

28、ll 40 ppm/C VDD= +15 V 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 6 DSCC FORM 2234

29、APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Feedthrough error FT VDD= +5 V 4, 5, 6 All 50 mV p-p VREF= 10 V, 4/ 5/ 100 kHz sinewave DB0-DB7 = 0 V; WR = CS = 0

30、V VDD= +15 V 50 Digital input capacitance CINVDD= +5 V 4 All 5 pF VIN= 0 V 6/ DB0-DB7 TA= +25C VDD= +15 V 20 VDD= +5 V 4 All 5 VIN= 0 V 6/ WR , CS TA= +25C VDD= +15 V 20 Output capacitance COUT1VDD= +5 V 4 All 120 pF DB0-DB7 = VDD; WR = CS = 0 V TA= +25C 6/ VDD= +15 V 120 COUT2VDD= +5 V 4 All 30 VDD

31、= +15 V 30 Output capacitance COUT1VDD= +5 V 4 All 30 pF DB0-DB7 = 0 V; WR = CS = 0 V TA= +25C 6/ VDD= +15 V 30 COUT2VDD= +5 V 4 All 120 VDD= +15 V 120 Chip select to write setup time tCS7/ VDD= +5 V 9, 10, 11 All 240 ns VDD= +15 V 150 Chip select to write hold time tCH7/ VDD= +5 V 9, 10, 11 All 0 n

32、s VDD= +15 V 0 Write pulse width tWRtCS tWR, tCH 0 VDD= +5 V 9, 10, 11 All 240 ns 7/ VDD= +15 V 150 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER C

33、OLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Data setup time tDS7/ VDD= +5 V 9, 10, 11

34、 All 170 ns VDD= +15 V 100 Data hold time tDH7/ VDD= +5 V 9, 10, 11 All 10 ns VDD= +15 V 10 Output current settling time tSL4/, 8/ VDD= +5 V 9, 10, 11 All 500 ns VDD= +15 V 350 1/ VOUT1= VOUT2= 0 V; VREF= +10 V unless otherwise specified. 2/ See 4.3.1d. 3/ Measured using internal feedback RFBand inc

35、ludes effect of leakage current and gain TC. 4/ Guaranteed, if not tested. 5/ Feedthrough error can be reduced by connecting the metal lid to ground. 6/ See 4.3.1c. 7/ Timing in accordance with figure 3. 8/ ROUT1load = 100, CEXT= 13 pF. WR , CS = 0 V, DB0-DB7 = 0 V to VDDor VDDto 0 V. Extrapolated:

36、tS(1/2 LSB) = tPD+ 6.2 T, where T = the measured first time constant of the final RC delay. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVIS

37、ION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device types 01, 02, and 03 Case outline E 2 Terminal number Terminal symbol 1 OUT 1 NC 2 OUT 2 OUT 1 3 GND OUT 24 DB7 (MSB) GND 5 DB6 DB7 (MSB) 6 DB5 NC 7 DB4 DB6 8 DB3 DB5 9 DB2 DB4 10 DB1 DB3 11 DB0 (LSB) NC 12 CS DB2 13 WR DB1 14 VDDDB0 (LSB) 15 VREFCS 1

38、6 RFBNC 17 - - - WR 18 - - - VDD19 - - - VREF20 - - - RFBFIGURE 1. Terminal connections. CS WR Mode DAC response L L Write DAC responds to data bus (DB0 - DB7) inputs H X Hold Data bus (DB0 - DB7) is locked out X H Hold DAC holds last data present when WR or CS assumed HIGH state L = Low state H = H

39、igh state X = Dont care FIGURE 2. Mode selection table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 9 DSCC FORM 2234 AP

40、R 97 NOTES: 1. All input signal rise and fall times measured from 10 percent to 90 percent to VDD. VDD= +5 V, tr= tf= 20 ns: VDD= +15 V, tr= tf= 40 ns. 2. Timing measurement reference level is 2V V ILIH +. 3. tDS+ tDHis approximately constant at 145 ns minimum at +25C, VDD= +5 V and tWR= 170 ns = 17

41、0 ns minimum. The devices are specified for a minimum tDHof 10 ns, however, in applications where tDH 10 ns, tDSmay be reduced accordingly up to the limit tDS= 65 ns, tDH= 80 ns. FIGURE 3. Write cycle timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

42、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87700 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical test

43、s for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where m

44、arking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendi

45、x A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an appro

46、ved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of c

47、onformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification

48、 and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on