DLA SMD-5962-87705 REV B-2005 MICROCIRCUITS BIPOLAR VMEBUS CONTROLLER MONOLITHIC SILICON《硅单块 VME总线双极微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Technical changes to table I. Editorial changes throughout. 90-08-08 W. Heckman B Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-11-21 Thomas M. Hess REV SHET REV B B B B B B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26

2、 27 28 29 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED Jeffery Tunstall DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR U

3、SE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, BIPOLAR, VMEbus AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 87-08-26 CONTROLLER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-87705 SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E502-05 Prov

4、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requ

5、irements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87705 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead fin

6、ish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 68172 VMEbus controller (BUSCON) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive des

7、ignator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range. -0.5 V dc to +7.0 V dc Storage temperature range . -65C to +150C Maximum power dissipation (PD

8、) 1/ 1.4 W Lead temperature (soldering, 5 seconds) +300C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC) 20C/W Thermal resistance, junction-to-ambient (JA) . 50C/W 1.4 Recommended operating conditions. Supply voltage: VCC. 4.75 V dc to 5.25 V dc VSS. 0 V High level input vo

9、ltage (logic inputs) (VIH) 2.0 V to VCCLow level input voltage (logic inputs) (VIL) . GND to 0.8 V dc Minimum high level output voltage 2.7 V dc Maximum low level output voltage. 0.5 V dc Frequency of operation . 25 MHz Case operating temperature range (TC) -55C to +125C _ 1/ Must withstand the adde

10、d PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLI

11、CABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTM

12、ENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK

13、-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Phila

14、delphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been

15、 obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and q

16、ualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qu

17、ality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to

18、 identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Termina

19、l connections. The terminal connections shall be as specified on figure 1. 3.2.3 Switching waveforms. The switching waveforms shall be as specified on figures 2 - 13. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as spec

20、ified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduct

21、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall

22、be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/complian

23、ce mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certif

24、icate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the man

25、ufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of ch

26、ange. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be

27、 made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 AP

28、R 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ 3/ -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min MaxDSI, ONBD, SLVN, VMEN, LBRN, RELSE, RESETN Input low current Input high current Input low voltage Input high voltage IILIIHVILVIHV1= 0.4

29、 V V1= 2.7 V 2.0 -400 20 0.8 A A V V ASN, MASN, BGINN, DTACKN, BERRN, LDTACKN, LBERRN Input low current Input high current Input low voltage Input high voltage IILIIHVILVIHV1= 0.4 V V1= 2.7 V 2.0 -400 20 0.8 A A V V R/WN, CLK Input low current Input high current Input low voltage Input high voltage

30、IILIIHVILVIHV1= 0.4 V V1= 2.7 V 2.0 -800 40 0.8 A A V V BGOUTN, VMEENN, SLVSELN, DSENN, DENN, DDIR (low current totem pole) Output low voltage Output high voltage VOLVOHIOL= 8 mA, VCC= 4.75 V IOH= -0.4 mA, VCC= 4.75 V 2.7 0.5 V V MASTENN (high current totem pole) Output low voltage Output high volta

31、ge VOLVOHIOL= 24 mA, VCC= 4.75 V IOH= -1.0 mA, VCC= 4.75 V 2.7 0.5 V V MASN (low current three-state) Output low voltage Output high voltage VOLVOHIOL= 8 mA, VCC= 4.75 V IOH= -0.4 mA, VCC= 4.75 V 2.7 0.5 V V ASN (high current three-state) Output low voltage Output high voltage VOLVOHIOL= 48 mA, VCC=

32、 4.75 V IOH= -3.0 mA, VCC= 4.75 V 2.7 0.5 V V LDTACKN, LBERRN, LBGN (low current open collector) Output low voltage Output leakage current VOLIOHIOL= 8 mA, VCC= 4.75 V VOUT= 5.25 V 1, 2, 3 0.6 100 V A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted

33、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ 3/ -55C TC +125C unless othe

34、rwise specified Refer- ence no. Group A subgroups Limits Unit Min Max DTACKN, BERRN, BRN, BBSYN (high current open collector) Output low voltage Output leakage current VOLIOHIOL= 48 mA, VCC= 4.75 V VOUT= 5.25 V 0.6 250 V A VCCsupply current ICCVCC= 5.25 V 1, 2, 3 250 mA Clock and general parameters

35、CLK cycle time (clk) CLK low time (clk) CLK high time (clk) t1t2t3See figures 2 to 11, 13. See figures 2 to 11, 13. See figures 2 to 11, 13. 1 2 3 40 15 15 ns ns ns Asynchronous input setup time to clk high ASN, MASN low ASN, MASN high SLVN, VMEN low SLVN, VMEN high ONBD low ONBD high LBRN, RELSE, B

36、GINN low LBRN, RELSE, BGINN high DSI low (end of slave cycle) t4t5t6t7t8t9t10t11t12See figures 2 to 6, 11, 13 4/See figures 2 to 4, 6 4/ See figures 2 to 6, 13 5/ See figures 4, 10, 11 5/ See figures 2, 3, 6 5/ See figure 11 5/ See figures 6, 9, 13 4/ See figures 7, 8 4/ See figures 4, 5, 6 4/ 4 5 6

37、 7 8 9 10 11 12 9, 10, 11 30 25 20 33 25 20 23 10 30 ns ns ns ns ns ns ns ns ns Asynchronous input hold time from clk high ASN, MASN, DSI ONBD, VMEN LBRN, RELSE, BGINN t13t14t156/ 7/ 6/ 9, 10, 11 0 0 2 ns ns ns Propagation, clk high to: BGOUTN low LBGN low LBGN high BBSYN, BRN low BBSYN, BRN high AS

38、N low ASN high SLVSELN, VMEENN low MASTENN t16t17t18t19t20t21t22t23t24See figure 9 See figure 13 See figures 6, 9, 13 See figures 6, 13 See figures 2, 3, 6 See figures 2, 3 See figures 4 to 6, 11, 13 See figures 6, 11, 13 16 17 19 20 21 22 23 24 9, 10, 11 20 20 11 17 14 12 14 19 55 70 46 53 34 41 40

39、 60 42 ns ns ns ns ns ns ns ns ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FO

40、RM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ 3/ -55C TC +125C unless otherwise specified Refer- ence no. Group A subgroups Limits Unit Min Max Miscellaneous RESETN width low BGINN high to BGOUTN high R/WN high to DSI high (start of read cyc

41、le) DSI low to R/WN low (end of read cycle) t25t27t28t298/ See figure 9 See figures 2, 4 9/ See figures 2, 5 9/ 27 28 29 9, 10, 11 6 clk 5 10 10 17 ns ns ns ns Address decoding SLVN high after DTACKN low VMEN, ONBD valid after MASN high MASN high DSI low ASN high t33t34t35t36t37See figure 10 See fig

42、ures 2, 3 9/ See figures 2, 3 10/ See figures 2, 3, 4 See figure 4 10/ 33 34 35 36 37 9, 10, 11 22 10 15 20 20 ns ns ns ns ns VMEbus acquisition ASN low to BGINN low (early release by other master) BBSYN low to BRN high ASN high to VMEENN low, DENN low (write) BBSYN or BGOUTN low to BGINN high t38At

43、40t42t43ASee figures 6, 13 9/ See figures 6, 13 See figure 6 11/ 12/ See figures 6, 9, 13 9/ 38A 40 42 43A 9, 10, 11 10 20 0 15 57 ns ns ns ns VMEbus master cycles ASN low to DSEN low R/WN low to DDIR high DDIR high toDENN low (write) DTACKN and BERRN high to DENN low (write, 1st bus cycle or preced

44、ed by read) DENN low to DSENN low (write) R/WN high to DDIR low DDIR low to DENN low (read) DSI high to DENN low (read) DSI high to DSENN low (read) DTACKN and BERRN high to DSENN low t46t47t48t49t50t51t52t53t54t55See figures 2, 3 13/ 14/ See figures 3, 6 See figures 3, 6 15/ See figure 3 15/ See fi

45、gure 3 13/ See figures 2, 4, 6 See figure 2 16/ See figure 2 16/ See figure 2 14/ See figures 2, 3 13/ 14/ 46 47 48 49 50 51 52 53 54 55 9, 10, 11 -1 2 14 clk + 13 13 7 10 14 15 14 36 11 41 2clk + 5340 26 30 45 51 ns ns ns ns ns ns ns ns ns ns See footnotes at end of table. Provided by IHSNot for Re

46、saleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87705 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Co

47、nditions 1/ 2/ 3/ -55C TC +125C unless otherwise specified Refer- ence no. Group A subgroups Limits Unit Min Max VMEbus master cycles DTACKN or BERRN low to LDTACKN or LBERRN low LDTACKN or LBERRN low to DSI or MASN high DSI low to DSENN high MASN high to DSENN high R/WN high to DSENN high (after a

48、write) MASN high to DENN high (read) DSI low to DENN high (read) R/WN high to DENN high (write) DSENN high to LDTACKN and LBERRN high DTACKN and BERRN high to LDTACKN and LBERRN high t56t57t58t59t60t62t63t64t65t66See figures 2, 3 See figures 2, 3 9/ See figures 2, 3 17/ See figures 2, 3 17/ See figure 3 18/ See figure 2 19/ See figure 2 19/ See figure 3 20/ See figures 2, 3 21/ See figures 2, 3 21/ 56 57 58 59 60 62 63 64 65 66 9, 10, 11 0 66 37 50 32 50 39 30 54 17 ns ns ns ns ns ns ns ns ns ns VMEbus release BBSYN low MASN high to VMEENN high or