DLA SMD-5962-87762 REV B-2011 MICROCIRCUIT LINEAR 8-BIT ANALOG-TODIGITAL CONVERTER WITH TRACK HOLD MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. Editorial changes throughout. drw 00-12-21 Raymond Monnin B Redraw. Update drawing to current requirements. - drw11-08-15 Charles F. SaffleTHE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED

2、. REV SHET REV SHET REV STATUS REV B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENT

3、S AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Ray Monnin APPROVED BY D. A. DiCenzo MICROCIRCUIT, LINEAR, 8-BIT, ANALOG-TO-DIGITAL CONVERTER, WITH TRACK/HOLD, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-07-25 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-87762 SHEET 1 OF 11 DSCC FORM

4、 2233 APR 97 5962-E427-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing

5、describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87762 01 V A Drawing number Device type (see 1.2.1) Case outlin

6、e(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 7575S Monolithic CMOS 8-bit A/D converter with track/hold amplifier, 5 s conversion time and 7-bit linearity 02 7575T Monolithic CMOS 8-bit

7、 A/D converter with track/hold amplifier, 5 s conversion time and 8-bit linearity 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 or CDIP2-T18 18 Dual-in-line2 CQCC1-N20 20 Square leadl

8、ess chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VDDto AGND . -0.3 V dc to +7.0 V dc VDDto DGND . -0.3 V dc to +7.0 V dc AGND to DGND . -0.3 V dc to VDDDigital input voltage to DGND (Pins CS , RD ) -0.3 V dc to VDDDigital

9、 input voltage to DGND: (Pins BUSY , DB0 to DB7) . -0.3 V dc to VDDCLK input voltage to DGND . -0.3 V dc to VDDVREFto AGND -0.3 V dc to VDDAIN to AGND . -0.3 V dc to VDDPower dissipation (PD) cases V and 2: Up to +75C . 450 mW Derate above +75C 6 mW/C Storage temperature range -65C to +150C Lead tem

10、perature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) (cases V and 2) . See MIL-STD-1835 Thermal resistance, junction-to-case (JA) (cases V and 2) . 120C/W Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU

11、IT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Ambient operating temperature range (TA) -55C to +125C Power supply voltage (VDD) . 5 V dc 5% Reference voltage (VREF) . 1.23 V dc AGND =

12、DGND 0 V dc External clock frequency (fCLK) . 4 MHz Analog input voltage range 0 V to 2 VREF(1 LSB = 2 VREF/256) 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified h

13、erein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Micr

14、ocircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quickse

15、arch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this docum

16、ent, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 RE

17、VISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufact

18、urer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. Thi

19、s QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance

20、 with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accorda

21、nce with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Functional diagram. The functional diagram shall be as specified on figure 2. 3.2.4 Timing test circuits and diagrams. The timing test circuits and diagrams shall be as specified on f

22、igure 3 and 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements s

23、hall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked.

24、 For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to M

25、IL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to

26、be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the re

27、quirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for a

28、ny change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at th

29、e option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance c

30、haracteristics. Test Symbol Conditions 1/ -55C TA +125C Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max Resolution RES All 8 Bits Total unadjusted error TUE 1 All -2 +2 LSB 2, 3 01 -2 +2 02 -1 +1 12 02 -1 +1 Relative accuracy RA 1 All -1 +1 LSB 2, 3 01 -1 +1 02 -0.5 +0.5

31、12 02 -0.5 +0.5 Full scale error AE 1, 2, 3 All -1 +1 LSB Offset error 2/ EOS 1, 2, 3 All -0.5 +0.5 LSB DC input impedance ZIH1, 2, 3 All 10 M Reference input current IREF1, 2, 3 All 500 A Digital input low voltage VILCS , RD , CLK 1, 2, 3 All 0.8 V Digital input high voltage VIHCS , RD , CLK 1, 2,

32、3 All 2.4 V Digital input current IINCS , RD , VIN= 0 V or VDD, 1 All -1 +1 A VDD= 5.25 V 2, 3 -10 +10 Digital input low current IILCLK; VIL= 0 V 1, 2, 3 All -800 +800 A Digital input high current IIHCLK; VIH= VDD1, 2, 3 All -800 +800 A Digital output low voltage VOLBUSY , DB0 to DB7, ISINK= 1.6 mA,

33、 VDD= 4.75 V 1, 2, 3 All 0.4 V Digital output high voltage VOHBUSY , DB0 to DB7, ISOURCE= -40 A, VDD= 4.75 V 1, 2, 3 All 4.0 V Floating state leakage current IOUTDB0 to DB7, VOUT= 0 V to VDD, VDD= 5.25 V 1, 2, 3 All -10 +10 A Power supply current 3/ IDD1, 2, 3 All 7 mA See footnotes at end of table.

34、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continue

35、d. Test Symbol Conditions 1/ -55C TA +125C Group A subgroupsDevice type Limits Unit unless otherwise specified Min Max Power supply rejection ratio PSRR 4.75 V VDD 5.25 V 1, 2, 3 All -0.25 +0.25 LSB Digital input capacitance CINCS , RD , TA= +25C, see 4.3.1c4 All 10 pF Floating state output capacita

36、nce COUTDB0 to DB7, TA= +25C, see 4.3.1c 4 All 10 pF Conversion time with external clock tCONVfCLK= 4 MHz, TA= +25C 4 All 5 s Slew rate, tracking SR TA= +25C 4 All 0.386 V/s Signal to noise ratio SNR VIN= 2.46 VP-Pat 10 kHz, TA= +25C 4 All 45 dB Conversion time with internal clock tCONVR = 100 k, CL

37、= 100 pF 9, 10, 11 All 5 15 s CS to RD , setup time, t1tWSCS See figure 4 9, 10, 11 All 0 ns RD to BUSY propagation tWPBD See figure 4 9 All 100 ns delay, t210, 11 120 Data access time after RD , t3 tDARSee figure 4 9 All 100 ns 4/ 10, 11 120 RD pulse width, t4tRDSee figure 4 9 All 100 ns 10, 11 120

38、 CS to RD hold time, t5tRHSSee figure 4 9, 10, 11 All 0 ns Data access time after tDABSee figure 4 9 All 80 ns BUSY , t64/ 10, 11 100 Data hold time, t75/ tDHSee figure 4 9 All 10 80 ns 10, 11 10 100 BUSY to CS delay, t8tBCDSee figure 4 9, 10, 11 All 0 ns 1/ The minimum resolution for which no missi

39、ng code is guaranteed is 8-bits. All input control signals are specified with tr= tf= 20 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V (see 1.4). VDD= +5 V, VREF= +1.23 V, unless otherwise specified. 2/ Offset error is measured with respect to an ideal code transition which occurs

40、at 0.5 LSB. 3/ Power supply current is measured when the device is inactive, i.e., when CS = RD = BUSY = logic HIGH. 4/ t3and t6, are measured with the load circuit of figure 3 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5/ t7is defined as the time required for the data l

41、ines to change 0.5 V when loaded with the circuits of figure 3 and is measured only for the initial test and after process or design changes which may affect t7. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596

42、2-87762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type 01 and 02 Case outline V 2 Terminal number Terminal symbol 1 CS CS 2 RD RD 3 TP TP4 BUSY BUSY 5 CLK CLK6 DB7 (MSB) DB7 (MSB) 7 DB6 DB6 8 DB5 DB59 DGND DGND 10 DB4 NC11 DB3 NC 12 DB2 DB4

43、13 DB1 DB3 14 DB0 (LSB) DB2 15 AGND DB116 AIN DB0 (LSB) 17 VREF AGND 18 VDD AIN 19 - - - VREF20 - - - VDDNC = no connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8776

44、2 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 FIGURE 2. Functional diagram. FIGURE 3. Timing test circuits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8

45、7762 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Timing diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87762 DLA LAND AND MARITIME COLUM

46、BUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be co

47、nducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be ma

48、de available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufactur