DLA SMD-5962-87786 REV B-2004 MICROCIRCUIT LINEAR 6-BIT VIDEO A D CONVERTER MONOLITHIC SILICON《硅单片6位视频A D模数转换器线性微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R056-93. 93-01-05 Michael A. Frye B Incorporate rev. A NOR. Update to current requirements. - drw 04-02-25 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS

2、 REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Charles E. Besore DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. H. Johnson COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROV

3、ED BY Michael A. Frye MICROCIRCUIT, LINEAR, 6-BIT VIDEO A/D AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-08-11 CONVERTER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-87786 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E116-04 DISTRIBUTION STATEMENT A. Ap

4、proved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR

5、97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87786 01 V A Drawing number

6、 Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 TDC1046 6-bit flash A/D converter 1.2.2 Case outline. The case outline is as designated in MIL-STD-183

7、5 and as follows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 or CDIP2-T18 18 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VCCto DGND. -0.5 V dc to +7.0 V dc VEEto AGND+0.5 V dc to -7.0 V dc

8、AGNDto DGND. -0.5 V dc to +0.5 V dc CONV, NMINV, or NLINV to DGND. -0.5 V dc to +5.5 V dc VIN, VRT, or VRBto AGND. +0.5 V dc to VEEVRTto VRB+1.2 V dc to -1.2 V Applied output voltage to DGND. -0.5 V dc to +5.5 V dc 1/ Applied output current, externally forced -1.0 mA to +6.0 mA 2/, 3/ Output short-c

9、ircuit duration . 1.0 s 4/ Storage temperature range. -65C to +150C Lead temperature (soldering, 10 seconds). +300C Power dissipation (PD) 1.0 W Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) 77.2C/W 1/ Applied voltage must be current limited

10、 to specified range. 2/ Forcing voltage must be limited to specified range. 3/ Current is specified as positive when flowing into the device. 4/ Single output in high state to ground. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

11、UIT DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Positive supply voltage (VCC). 4.5 V dc to 5.5 V dc Negative supply voltage (VEE). -4.9 V dc to -5.5 V dc Analog ground voltage

12、to DGND(VAGND) . -0.1 V dc to +0.1 V dc CONV pulse width, low (tPWL). 15 ns minimum CONV pulse width, high (tPWH). 17 ns minimum Input voltage, logic low (VIL) 0.8 V dc maximum Input voltage, logic high (VIH) 2.0 V dc minimum Output current, logic low (IOL) . 2.0 mA maximum Output current, logic hig

13、h (IOH) . -0.4 mA maximum Most positive reference input (VRT) 5/. -0.1 V dc to 0.1 V dc Most negative reference input (VRB) 5/ . -0.9 V dc to -1.1 V dc Voltage reference differential (VRT- VRB) 0.8 V dc to 1.2 V dc Input voltage (VIN) VRBto VRTCase operating temperature range. -55C to +125C 2. APPLI

14、CABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defen

15、se Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MI

16、L-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available f

17、rom the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, howev

18、er, supersedes applicable laws and regulations unless a specific exemption has been obtained. 5/ VRTmust be more positive than VRB, and VRT- VRBmust be within the specified range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

19、DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as spe

20、cified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approve

21、d program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall no

22、t affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-385

23、35, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Truth table. The truth tab

24、le shall be as specified on figure 3. 3.2.5 Timing diagram. The timing diagram shall be as specified on figure 4. 3.2.6 Load circuit. The load circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characte

25、ristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking s

26、hall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For packages where marking of the entire SMD PIN number is not feasible due to space lim

27、itations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “Q

28、ML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certifica

29、te of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-3853

30、5, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535, appendix A. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain th

31、e option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING S

32、IZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Device type Limits Unit Min MaxPositive suppl

33、y current, static ICCVEE= -4.9 V, VCC= 5.5 V 1, 2, 3 01 25 mA Negative supply current, static IEEVEE= -5.5 V 1, 3 01 -150 mA 2 -92 Reference current IREFVRT= 0 V, VRB= -1.0 V, VEE= -4.9 V 1, 2, 3 01 15 mA Input constant bias current ICBVEE= -5.5 V, VCC= 5.5 V 1, 2, 3 01 180 A Input low current IILCO

34、NV 1, 2, 3 01 -0.6 mA VI= 0.4 V, VEE= -4.9 V, VCC= -4.9 V NMINV, NLINV -0.8 Input high current IIHVI= 2.4 V, VCC= 5.5 V, VEE= -4.9 V 1, 2, 3 01 50 A Input current at maximum input voltage IIVI= 5.5 V, VCC= 5.5 V, VEE= -4.9 V 1, 2, 3 01 1.0 mA Output low voltage VOLIOL= 2 mA, VCC= 4.5 V, VEE= -5.5 V

35、1, 2, 3 01 0.5 V Output high voltage VOHIOH= -400 A, VCC= 4.5 V 1, 2, 3 01 2.4 V Output short circuit current 2/ IOSVEE= -4.9 V, VCC= 5.5 V 1, 2, 3 01 -30 mA Digital output delay tDVEE= -4.9 V, VCC= 5.5 V See figures 4 and 5 9, 10, 11 01 35 ns Linearity error integral, independent ELIVRT= 0 V, VRB=

36、-1.0 V, FS = 100 kHz 4, 5, 6 01 0.4 % Linearity error integral, differential ELDVRT= 0 V, VRB= -1.0 V, FS = 100 kHz 4, 5, 6 01 0.4 % Functional tests FT VEE= -4.9 V, VCC= 4.5 V f = 1.0 MHz, see 4.3.1b 7, 8 01 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking p

37、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test 3/ Symbol Conditions -55C TC +125C 1/ unless

38、 otherwise specified Group A subgroups Device type Limits Unit Min MaxOffset error, top EOTVIN= midpoint of code 0 1, 2, 3 01 +50 mV Offset error, bottom EOBVIN= midpoint of code 63 1, 2, 3 01 -30 mV Total reference resistance RREFVRT= 0 V, VRB= -1.0 V 1, 2, 3 01 66 Input equivalent resistance RINVR

39、T= 0 V, VRB= -1.0 V 1, 2, 3 01 40 k Input capacitance CINVRT= 0 V, VRB= -1.0 V 4, 5, 6 01 30 pF Digital input capacitance CITC= +25C, F = 1 MHz 4 01 15 pF Maximum conversion rate FS 4, 5, 6 01 25 MSPS Sampling time offset tSTOSee figures 4 and 5 9, 10, 11 01 15 ns Output hold time tHOSee figures 4 a

40、nd 5 9, 10, 11 01 5 ns Code size Q 01 50 150 % of nominal Temperature coefficient offset voltage TCO1, 2, 3 01 20 V/C Bandwidth, full power input BW 4, 5, 6 01 12.5 MHz Signal-to-noise ratio (25 MSPS conversion rate, SNR 1 MHz input 4, 5, 6 01 42 dB 12.5 MHZ bandwidth) Peak to Peak signal/ RMS noise

41、 12.5 MHz input 38 1 MHz input 33 RMS signal/ RMS noise 12.5 MHz input 29 1/ Unless otherwise specified, characteristics apply over the recommended operating conditions specified in 1.4 herein. 2/ Output high, one pin to ground, one second duration maximum. 3/ These tests are guaranteed if not teste

42、d. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outline V Terminal number T

43、erminal symbol 1 VIN2 RT3 DGND4 NMINV 5 MSB D16 D27 D38 VCC9 VEE10 VCC11 NLINV 12 D413 D514 D6(LSB) 15 CONV 16 DGND17 AGND18 RBFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-8

44、7786 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 FIGURE 2. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87786 DEFENSE SUPPLY CENTE

45、R COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 Binary Offset twos complement Step Range True Inverted True Inverted -1.0000 V Fs NMINV = 1 0 0 1 15.8730 mV step NLINV = 1 0 1 0 00 0.0000 V 000000 111111 100000 011111 01 -0.0159 V 000001 111110 100001 011110 “ “ “

46、 “ “ “ “ “ “ “ “ “ 31 -0.4921 V 011111 100000 111111 000000 32 -0.5079 V 100000 011111 000000 111111 33 -0.5238 V 100001 011110 000001 111110 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 62 -0.9841 V 111110 000001 011110 100001 63 -1.0000 V 111111 000000 011111 100000 NOTES: 1. NMINV and NLINV are to be cons

47、idered dc controls. They may be tied to +5.0 V for a logic “1” and tied to ground for a logic “0”. 2. Voltages are code midpoints when calibrated by adjusting VRTand VRBto set the 1stand 63rdthresholds to the desired voltages. Note that R1is greater than R (refer to block diagram on figure 2 herein)

48、, ensuring calibration with a positive voltage on RT. Assuming a 0 V to 1.0 V desired range, continuously strobe the converter with 0.0079 V (1/2 LSB from 0 V) on the analog input, and adjust VRTfor output toggling between 00 and 01. Then apply 0.9921 V (1/2 LSB from 1.0 V) and adjust VRBfor toggling between codes 62 and 63. The degree of required adjustment is indicated by the offset error, EOTand EOB. Offset errors are generated by the inherent parasitic resistance between the package pin and the actual resistor chain on the integrated circuit. These parasitic resistors are shown as R1