DLA SMD-5962-87802 REV D-2011 MICROCIRCUIT LINEAR 8-BIT QUAD DIGITAL-TO- ANALOG CONVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case 2 for vendor CAGE 06665 and vendor CAGE 24355. Change to Standardized Military Drawing CAGE code 67268. Add testing at temperature for dynamic and ac tests. Editorial changes throughout.90-01-30 M. A. Frye B Changes in accordance with NO

2、R 5962-R006-94. 93-10-15 M. A. Frye C Drawing updated to reflect current requirements. Editorial changes throughout. drw 01-02-21 Raymond Monnin D Redraw. Update paragraphs to new boilerplate requirements. - drw 11-11-07 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. C

3、URRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Joseph A. Kerby DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY A

4、LL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-BIT QUAD DIGITAL-TO-ANALOG CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-06-01 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 14933 5962-87802 SHEET 1 OF 10

5、DSCC FORM 2233 APR 97 5962-E486-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This

6、 drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87802 01 R A Drawing number Device type (see 1.2.1) Ca

7、se outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 7226 Four 8-bit digital-to-analog converters with output amplifiers 1.2.2 Case outlines. The case outlines are as designated in MI

8、L-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ VDDto AGND or DG

9、ND -0.3 V dc to +17.0 V dc VDDto VSS-0.3 V dc to +24.0 V dc AGND to DGND . -0.3 V dc to VDDDigital input voltage to DGND -0.3 V dc to VDDVREFto AGND -0.3 V dc to VDDVOUTto AGND 2/ VSSto VDDStorage temperature range -65C to +150C Maximum power dissipation (PD) . 500 mW 3/ Lead temperature (soldering,

10、 10 seconds) +300C Thermal resistance, junction-to-case (JC): Cases R and 2 . See MIL-STD-1835 Junction temperature (TJ) +150C 1.4 Recommended operating conditions. Power supply range (VDD) +11.4 V dc to +16.5 V dc Input reference voltages: Dual supply operation +2.0 V dc to VDD-4 V dc Single supply

11、 operation +10.0 V dc Ambient operating temperature range (TA) -55C to +125C _ 1/ Unless otherwise specified all voltages are referenced to ground. 2/ Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA.

12、3/ For temperatures above +75C derate linearly at 2.0 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97

13、 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract

14、. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS

15、 MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5

16、094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUI

17、REMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufactur

18、er or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (Q

19、M) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the

20、QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. Th

21、e terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herei

22、n, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are des

23、cribed in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characte

24、ristics (dual supply). Test Symbol Conditions 1/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Supply current from VDDIDDOutputs unloaded, VIN= VINLor VINH1, 2, 3 All 13.0 mA Supply current from VSSISSOutputs unloaded, VIN= VINLor VINH1, 2, 3 All 11.0 mA R

25、eference voltage VREF1, 2, 3 All 2.0 VDD- 4 V Reference input resistance RI1, 2, 3 All 2 k Reference input capacitance CINEach DAC loaded with all 1s see 4.3.1c 4 All 300 pF Total unadjusted error VDD= +15 V 5%, VREF= +10 V 1, 2, 3 All 2 LSB Relative accuracy 1, 2, 3 All 1 LSB Differential nonlinear

26、ity Guaranteed monotonic 1, 2, 3 All 1 LSB Full scale error 1, 2, 3 All 1.5 LSB Zero code error 1, 2, 3 All 30 mV Input high voltage VINH1, 2, 3 All 2.4 V Input low voltage VINL1, 2, 3 All 0.8 V Input leakage current IlkgVIN= 0 V or VDD1, 2, 3 All 1 A Functional tests See 4.3.1d 7 All Voltage output

27、 slew rate 2/ SR 4, 5, 6 All 2.5 V/s Voltage output settling time (pos. full scale change) 2/ ttotSettling time to 1/2 LSB VREF= +10 V 4, 5, 6 All 5.0 s Voltage output settling time (neg. full scale change) 2/ ttotSettling time to 1/2 LSB VREF= +10 V 4, 5, 6 All 7.0 s Load resistance ROVOUT= +10 V 4

28、 All 2.0 k Address to write setup time tAS 9, 10,11 All 0.0 ns Address to write hold time tAH 10,11 All 10.0 ns Data valid to write setup tDS 9 All 90 ns time 10,11 100 Data valid to write hold time tDH9, 10, 11 All 10.0 ns Write pulse width tWR9 All 150 ns 10, 11 250 See footnotes at end of table.

29、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics (single sup

30、ply) - continued. Test Symbol Conditions 3/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Supply current from VDDIDDOutputs unloaded, VIN= VINLor VINH1, 2, 3 All 13.0 mA Reference input resistance RI1, 2, 3 All 2 k Reference input capacitance CINEach DAC l

31、oaded with all 1s see 4.3.1c 4 All 300 pF Total unadjusted error 1, 2, 3 All 2 LSB Differential nonlinearity Guaranteed monotonic 1, 2, 3 All 1 LSB Input high voltage VINH1, 2, 3 All 2.4 V Input low voltage VINL1, 2, 3 All 0.8 V Input leakage current IlkgVIN= 0 V or VDD1, 2, 3 All 1 A Functional tes

32、ts See 4.3.1d 7 All Voltage output slew rate 2/ SR 4, 5, 6 All 2.0 V/s Voltage output settling time (pos. full scale change) 2/ ttotSettling time to 1/2 LSB VREF= +10 V 4, 5, 6 All 5.0 s Voltage output settling time (neg. full scale change) 2/ ttotSettling time to 1/2 LSB VREF= +10 V 4, 5, 6 All 20.

33、0 s Load resistance ROVOUT= +10 V 4 All 2.0 k Address to write setup time tAS 9, 10,11 All 0.0 ns Address to write hold time tAH 10,11 All 10.0 ns Data valid to write setup tDS 9 All 90 ns time 10,11 100 Data valid to write hold time tDH9, 10, 11 All 10.0 ns Write pulse width tWR9 All 150 ns 10, 11

34、250 1/ VDD= 11.4 V to 16.5 V; VSS= -5 V 10%; AGND = DGND = 0.0 V; VREF= 2 V to (VDD 4 V) (unless otherwise specified). 2/ Guaranteed if not tested to the limits specified. 3/ VDD= +15 V 5%; VSS= AGND = DGND = 0.0 V; VREF= +10 V (unless otherwise specified). Provided by IHSNot for ResaleNo reproducti

35、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outline R and 2 Terminal number Terminal symbol 1 VOUTB 2 VOUTA 3 VSS4 VREF5 AGND

36、 6 DGND 7 DB7 (MSB) 8 DB6 9 DB510 DB4 11 DB312 DB2 13 DB114 DB0 (LSB) 15 WR16 A1 17 A0 18 VDD19 VOUTD 20 VOUTC FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AN

37、D MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Control inputs Operation WRA1 A0 H X X No operation device not selected L L L DAC A transparent L L DAC A latched L L H DAC B transparent L H DAC B latched L H L DAC C transparent H L DAC C latched L H H DAC D transp

38、arent H H DAC D latched L = Low state, H = High state, X = Dont care FIGURE 2. Truth table. FIGURE 3. Functional block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLU

39、MBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire

40、 SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance

41、indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply

42、 in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of con

43、formance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9

44、Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION

45、 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additi

46、onal criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit s

47、hall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter

48、 tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87802 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (metho