DLA SMD-5962-88535 REV D-2008 MICROCIRCUIT DIGITAL CMOS 4-BIT SLICE MICROPROCESSOR MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A 1.3, Absolute maximum ratings, changed DC input voltage minimum limit. 1.4, Recommended operating conditions, changed input low voltage minimum limit. Table I, tPWH, device 02, maximum limit corrected. Table I, footnote 1/, 30 seconds changed to

2、1 second. Editorial changes throughout. 95-04-13 William K. Heckman B Add device type 03. Update boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout. - LTG 02-06-10 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requierements. - CFS 08-02-05 Thomas M. Hess D

3、Change the minimum limits of device type 03 for IIX and IOZ parameters in table I on sheet 5 from -200 A to -220 A. - CFS 08-10-17 Thomas M. Hess REV SHEET REV C C C C C C C SHEET 15 16 17 18 19 20 21 REV D C C C D C C C C C C C C C REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/

4、A PREPARED BY Todd D. Creek CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 88-05-26 MICROCIRCUIT, DIGITAL, CMOS, 4-BIT SLICE MICROPROCESSOR, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-88535 S

5、TANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LEVEL D SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E010-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZ

6、E A 5962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PR

7、F-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88535 01 Q X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows:

8、Device type Generic number Circuit function Cycle time 01 7C901-32, 39C01C 4-bit microprocessor slice 32 ns 02 7C901-27, 39C01D 4-bit microprocessor slice 27 ns 03 7C901-35 4-bit microprocessor slice 35 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: O

9、utline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line X CQCC1-N44 44 Square leadless chip carrier Y See figure 1 42 Flat pack 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply volta

10、ge range -0.5 V dc to +7.0 V dc DC voltage applied to output in high Z state. -0.5 V dc to +7.0 V dc DC input voltage. -0.5 V dc to +7.0 V dc DC output current. 30 mA Maximum power dissipation (PD) 1.0 W 2/ Storage temperature range -65C to +150C Thermal resistance, junction-to-case (JC): Cases Q an

11、d X See MIL-STD-1835 Case Y. 10C/W Lead temperature (soldering, 10 seconds). +300C Maximum junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input high voltage (VIH). 2.0 V dc to 6.0 V dc Input low voltage (VIL). -0.5 V dc to +0

12、.8 V dc Case operating temperature range (TC) . -55C to +125C _ 1/ Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated on the operational sections of th

13、is specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5

14、962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this dr

15、awing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-

16、883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at htt

17、p:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the t

18、ext of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN

19、 class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordan

20、ce with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the dev

21、ice. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions sha

22、ll be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagr

23、am shall be as specified on figure 3. 3.2.4 AC loading test circuits. The AC loading test circuits shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply

24、over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

25、ut license from IHS-,-,-SIZE A 5962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in

26、1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “

27、C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q” or “QML” certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used 3.6 Certificate of compliance. A certificate

28、 of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requi

29、rements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DS

30、CC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the opt

31、ion of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performan

32、ce characteristics. Limits Test Symbol Conditions +4.5 V VCC +5.5 V -55C TC +125C unless otherwise specified Devicetype Group A subgroups Min Max Unit Input high voltage VIHAll 1, 2, 3 2.0 V Input low voltage VILAll 1, 2, 3 0.8 V Output high voltage VOHVCC= 4.5 V, IOH= -3.4 mA All 1, 2, 3 2.4 V Outp

33、ut low voltage VOLVCC= 4.5 V, IOL= 16.0 mA All 1, 2, 3 0.4 V 01, 02 -10 +10 Input leakage current IIXVCC= 5.5 V GND VIN VCC 03 1, 2, 3 -220 +10 A 01, 02 -40 +40 Output leakage current IOZVCC= 5.5 V GND VOUT VCC 03 1, 2, 3 -220 +40 A Output short circuit current 1/ IOSVCC= 5.5 V, VOUT= GNDAll 1, 2, 3

34、 -30 -85 mA Operating supply current ICC1 VCC= 5.5 V, fCP= 10 MHz VIL= 0.8 V, VIH= 2.0 V CP = 50% duty cycle All 1, 2, 3 90 mA Dynamic supply current ICC2 VCC= 5.5 V, fCP= 10 MHz VIL= 0.4 V, VIH= 4.3 V CP = 50% duty cycle All 1, 2, 3 31 mA Input capacitance CIN12 Output capacitance COUTAll 15 Input/

35、output capacitance CI/OSee 4.3.1c VCC= 5.0 V 2/ 03 4 20 pF Functional test See 4.3.1d All 7, 8 01 32 02 9, 10, 11 25 9, 11 32 A setup time to positive edge of clock 4/ tS103 10 40 ns 01, 03 15 A setup time to negative edge of clock 4/ tS202 9, 10, 11 12 ns 01 32 02 9, 10, 11 25 9, 11 32 B (source) s

36、etup time to positive edge of clock 4/ tS303 10 40 ns 01, 03 15 B (source) setup time to negative edge of clock 4/ tS4See figure 4. 3/ 02 9, 10, 11 12 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-88535

37、 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions +4.5 V VCC +5.5 V -55C TC +125C unless otherwise specified Devicetype Grou

38、p A subgroups Min Max Unit 01, 03 15 B (destination) setup time to negative edge of clock tS502 9, 10, 11 12 ns 01 25 02 9, 10, 11 16 9, 11 25 Data setup time to positive edge of clock tS603 10 35 ns 01 20 02 9, 10, 11 13 9, 11 20 Cnsetup time to positive edge of clock tS703 10 25 ns 01, 03 30 I0, 1

39、, 2setup time to positive edge of clock tS802 9, 10, 11 19 ns 01, 03 30 I3, 4, 5setup time to positive edge of clock tS902 9, 10, 11 19 ns 01, 03 10 I6, 7, 8setup time to negative edge of clock tS1002 9, 10, 11 9 ns 01 12 02 9, 10, 11 9 9, 11 12 RAM0, 3, Q0, 3setup time to positive edge of clock tS1

40、103 10 15 ns 01, 03 2 A hold time from positive edge of clock 5/ tH102 9, 10, 11 2 ns 01, 03 2 A hold time from negative edge of clock 5/ tH202 9, 10, 11 2 ns 01, 03 2 B (source) hold time from positive edge of clock 5/ tH302 9, 10, 11 2 ns 01, 03 2 B (source) hold time from negative edge of clock 5

41、/ tH4See figure 4. 3/ 02 9, 10, 11 2 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 D

42、SCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions +4.5 V VCC +5.5 V -55C TC +125C unless otherwise specified Devicetype Group A subgroups Min Max Unit 01, 03 2 B (destination) hold time from positive edge of clock tH502 9, 10, 11 2 ns 01,

43、 03 0 Data hold time from positive edge of clock tH602 9, 10, 11 0 ns 01, 03 0 Cnhold time from positive edge of clock tH702 9, 10, 11 0 ns 01, 03 0 I0, 1, 2hold time from positive edge of clock tH802 9, 10, 11 0 ns 01, 03 0 I3, 4, 5hold time from positive edge of clock tH902 9, 10, 11 0 ns 01, 03 0

44、 I6, 7, 8hold time from positive edge of clock tH1002 9, 10, 11 0 ns 01, 03 0 RAM0, 3, Q0, 3hold time from positive edge of clock tH1102 9, 10, 11 0 ns 01, 03 48 Delay from A to Y tP1 02 9, 10, 11 33 ns 01, 03 48 Delay from A to F3 tP2 02 9, 10, 11 33 ns 01, 03 48 Delay from A to Cn+4 tP3 02 9, 10,

45、11 33 ns 01, 03 44 Delay from A to G and P tP4 02 9, 10, 11 33 ns 01 48 02 9, 10, 11 33 9, 11 48 Delay from A to F = 0tP5 03 10 55 ns 01, 03 48 Delay from A to OVRtP6 02 9, 10, 11 33 ns 01, 03 48 Delay from A to RAM0, RAM3 tP7 See figure 4. 3/ 02 9, 10, 11 33 ns See footnotes at end of table. Provid

46、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-88535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Contin

47、ued. Limits Test Symbol Conditions +4.5 V VCC +5.5 V -55C TC +125C unless otherwise specified Devicetype Group A subgroups Min Max Unit 01, 03 48 Delay from B to Y tP8 02 9, 10, 11 33 ns 01, 03 48 Delay from B to F3 tP9 02 9, 10, 11 33 ns 01, 03 48 Delay from B to Cn+4 tP10 02 9, 10, 11 33 ns 01, 03

48、 44 Delay from B to G and P tP11 02 9, 10, 11 33 ns 01 48 02 9, 10, 11 33 9, 11 48 Delay from B to F = 0tP12 03 10 55 ns 01, 03 48 Delay from B to OVRtP13 02 9, 10, 11 33 ns 01, 03 48 Delay from B to RAM0, RAM3 tP14 02 9, 10, 11 33 ns 01, 03 37 Delay from data to Y tP15 02 9, 10, 11 24 ns 01, 03 37 Delay from data to F3 tP16 02 9, 10, 11 23 ns 01, 03 37 Delay from data to Cn+4 tP17 02 9, 10, 11 23 ns 01, 03 34 Delay from data to G and P tP18 02 9, 10, 11 21 ns 01 40 02 9, 10, 11 25 9, 11 40 Delay from data to F = 0tP19 03 10 45 ns 01, 03 37 Delay from