DLA SMD-5962-88544 REV C-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 256K X 1 STATIC RAM (SRAM) LOW POWER MONOLITHIC SILICON《硅单片256K X 1低功耗静态存取存储器互补型金属氧化物半导体数字存储微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added case outline letter Y. Added CAGE numbers 6Y440 and 75569 for devices 01 through 04. Editorial changes throughout. 91-11-05 M. A. Frye B Changes in accordance with NOR 5962-R144-92 92-02-13 M. A. Frye C Boilerplate update, part of 5 year re

2、view. ksr 06-11-20 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV C SHET 15 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT D

3、RAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY DA DiCenzo AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-08-01 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 256K X 1 STATIC RAM (SRAM) LOW

4、POWER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-88544 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E006-07 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY CEN

5、TER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The

6、complete PIN is as shown in the following example: 5962-88544 01 L A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Acess time 01 25

7、6K X 1 low power CMOS static ram 35 ns 02 256K X 1 low power CMOS static ram 45 ns 03 256K X 1 low power CMOS static ram 55 ns 04 256K X 1 low power CMOS static ram 70 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designato

8、r Terminals Package style L GDIP3-T24 or CDIP4-T24 24 dual-in-line package X CQCC3-N28 28 rectangular chip carrier package Y CDFP4-F28 28 flat package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Voltage on any input relative to VSS -

9、0.5 V dc to +7.0 V dc Voltage applied to Q - -0.5 V dc to +6.0 V dc Storage temperature range - -65C to +150C Maximum power dissipation (PD) - 1.0 W Lead temperature (soldering, 10 seconds) - +260C Thermal resistance, junction-to-case (JC): Cases L, X, and Y - See MIL-STD-1835 Junction temperature (

10、TJ) - +150C 2/ 1.4 Recommended operating conditions. Supply voltage range (VCC) - 4.5 V dc to 5.5 V dc Supply voltage range (VSS) - 0 V dc Input high voltage (VIH) - 2.2 V dc to +6.0 V dc Input low voltage (VIL) - -0.5 V dc to +0.8 V dc 3/ Case operating temperature range (TC) - -55C to +125C 1/ Gen

11、eric numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method

12、5004 of MIL-STD-883. 3/ VILminimum = -3.0 V dc for pulse width less than 20 ns. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C

13、SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in

14、 the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DE

15、PARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk,

16、700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulation

17、s unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manu

18、facturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535.

19、 This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accord

20、ance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in acc

21、ordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle prot

22、ection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approv

23、ed by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

24、 as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo r

25、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Conditions Limits Test Symbol -55C

26、 TC +125C Group A Device Unit VCC= 4.5 V to 5.5 V subgroups types VSS= 0 V Min Max unless otherwise specified Operating supply current ICC1tAVAV= tAVAV(minimum), 1,2,3 All 100 mA 1/ VCC= 5.5 V, CE = VIL, all other inputs at VIL Standby power supply ICC2CE VIH, all other inputs 1,2,3 All 25 mA curren

27、t TTL 1/ VILor VIH, VCC= 5.5 V f = 0 MHz Standby power supply ICC3CE (VCC-0.2 V), f = 0 MHz, 1,2,3 All 3 mA current CMOS 1/ VCC= 5.5 V, all other inputs 0.2 V or (VCC-0.2 V) Data retention current ICC4 VCC= 2.0 V 1,2,3 All 900 A 1/ Input leakage current, IILKVCC= 5.5 V, 1,2,3 All 10 A any input VIN=

28、 0 V to 5.5 V Off-state output leakage IOLKVCC= 5.5 V, 1,2,3 All 10 A current VIN= 0 V to 5.5 V Data retention voltage VDRVIN 0.2 V or (VCC-0.2 V), 1,2,3 All 2.0 V CE (VCC-0.2 V) Output high voltage VOHIOUT= -4.0 mA, VCC= 4.5 V, 1,2,3 All 2.4 V VIL= 0.8 V, VIH= 2.2 V Output low voltage VOLIOUT= 8.0

29、mA, VCC= 4.5 V, 1,2,3 All 0.4 V VIL= 0.8 V, VIH= 2.2 V Input capacitance CINVIN= 0 V, f = 1.0 MHz, 4 All 10.0 pF TC= +25C, see 4.3.1c Output capacitance COUTVO= 0 V, f = 1.0 MHz, 4 All 12.0 pF TC= +25C, see 4.3.1c See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network

30、ing permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55C TC +125C

31、Group A Device Unit VCC= 4.5 V to 5.5 V subgroups types VSS= 0 V 2/ Min Max unless otherwise specified Chip enable access time tELQVSee figure 4 9,10,11 01 35 ns 02 45 03 55 04 70 Read cycle time tAVAVSee figure 4 3/ 9,10,11 01 35 ns 02 45 03 55 04 70 Address access time tAVQVSee figure 4 4/ 9,10,11

32、 01 35 ns 02 45 03 55 04 70 Output hold after tAVQXSee figure 4 9,10,11 All 3.0 ns address change Chip enable to output tELQXSee figure 4 5/ 6/ 9,10,11 All 3.0 ns active Chip disable to output tEHQZSee figure 4 5/ 6/ 9,10,11 01,02 0 20 ns inactive 03 0 25 04 0 30 Chip enable to power up tELPUSee fig

33、ure 4 5/ 9,10,11 All 0 ns Chip enable to power tEHPDSee figure 4 5/ 9,10,11 01 35 ns down 02 45 03 55 04 70 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY

34、CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55C TC +125C Group A Device Unit VCC= 4.5 V to 5.5 V subgroups types VSS= 0 V 2/ Min Max unless otherwise specified Wri

35、te cycle time tAVAVSee figure 5 9,10,11 01 35 ns 02 45 03 55 04 70 Write pulse width tWLWHSee figure 5 9,10,11 01 30 ns 02 40 03 50 04 55 Chip enable to end of tELEHSee figure 5 9,10,11 01 30 ns write 02 40 03 50 04 55 Data setup to end of tDVWHSee figure 5 9,10,11 01,02 20 ns write 03,04 25 Data ho

36、ld after end of tWHDXSee figure 5 9,10,11 All 0 ns write Address setup to end of tAVWHSee figure 5 9,10,11 01 30 ns write 02 40 03 50 04 55 Address setup to tAVWLSee figure 5 9,10,11 All 0 ns beginning of write (write cycle number 1) tAVELSee figure 5 9,10,11 All 0 ns (write cycle number 2) Address

37、hold after end tWHAVSee figure 5 9,10,11 All 5.0 ns of write See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVIS

38、ION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55C TC +125C Group A Device Unit VCC= 4.5 V to 5.5 V subgroups types VSS= 0 V 2/ Min Max unless otherwise specified Write enable to output tWLQZSee figure 5 5/ 6/ 9,10,11 01 0 15 ns disable 02 0 20 03 0 25 04 0 30 Output active after tWHQXSee figure 5 5/ 6/ 7/ 9,10,11 All 0 ns end of write Deselect time tEHVCCL See figure 6 5/ 8/ 9,10,11 All tAVAV ns (m