DLA SMD-5962-88663 REV B-2013 MICROCIRCUIT LINEAR OCTAL VOLTAGE MODE 8-BIT D A CONVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. - drw 02-04-25 Raymond Monnin B Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-12-13 Charles F. Saffle THE FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS

2、REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Charles E. Besore DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF D

3、EFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, OCTAL, VOLTAGE MODE, 8-BIT D/A CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-01-24 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-88663 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E088-14 Provided by I

4、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-S

5、TD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88663 01 L A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1

6、.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function Total unadjusted error 01 7228T Octal, CMOS, 8-bit voltage-mode DAC 2.0 LSB 02 7228U Octal, CMOS, 8-bit voltage-mode DAC 1.0 LSB 1.2.2 Case outlines. The case outlines are as des

7、ignated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VDDto

8、ground range -0.3 V dc to +17 V dc VDDto VSSrange +0.3 V dc to +24 V dc Digital input voltage to ground range . -0.3 V dc to VDDVREFto ground range . -0.3 V dc to VDDVOUTto ground range 1/ . VSSto VDDStorage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipa

9、tion (PD) . 1.0 W 2/ Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Operating voltage range for dual supply: Positive supply range (VDD) +10.8 V dc to +16.5 V dc Negative supply range (VSS) -4.5 V dc to -5.5 V dc Ref

10、erence voltage range (VREF) . +2.0 V dc to +10.0 V dc Operating voltage range for dual supply: Positive supply range (VDD) +13.5 V dc to +16.5 V dc Negative supply range (VSS) 0 V dc Reference voltage range (VREF) . +10 V dc Ambient operating temperature range (TA) -55C to +125C _ 1/ Outputs may be

11、shorted to any voltage in the range VSSto VDDprovided that the power dissipation is not exceeded. Typical short circuit current for a short to ground or VSSis 50 mA. 2/ Derate above TA= +75C at 2.0 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

12、,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this d

13、rawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD

14、-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at ht

15、tp:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Not

16、hing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified h

17、erein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved progra

18、m plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect

19、 the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appe

20、ndix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics

21、. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electric

22、al tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number

23、is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” sh

24、all be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIM

25、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Total unadjusted error 2/ TUE1 VDD= 15 V 10%, VREF= +10 V,

26、1, 2, 3 01 2.0 LSB single supply only 1 02 2.0 2, 3, 12 1.0 Total unadjusted error 2/, 3/ TUE2 VREF= +10 V, dual supply only 1, 2, 3 01 2.0 LSB 1 02 2.0 2, 3, 12 1.0 Relative accuracy RA 1, 2, 3 01 1.0 LSB 1 02 1.0 2, 3, 12 0.5 Differential nonlinearity DNL1 Guaranteed monotonic, single supply only

27、1, 2, 3 All 1.0 LSB Differential nonlinearity 3/ DNL2 Dual supply only 1, 2, 3 All 1.0 LSB Full scale error 4/ FSE 1, 2, 3 01 1.0 LSB 1 02 1.0 2, 3, 12 0.5 Zero code error ZCE 1 All 25 mV 2, 3 01 30 02 20 12 02 15 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or network

28、ing permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherw

29、ise specified Group A subgroups Device type Limits Unit Min Max Load resistance RLVOUT= 10 V, dual and single supply 1, 2, 3 All 2.0 k Reference input voltage range VREF1, 2, 3 All 2.0 10 V Reference resistance RINDual supply only 1, 2, 3 All 2.0 k Reference input capacitance 5/ CIN (REF) Dual and s

30、ingle supply,TA= +25C 4 All 500 pF Digital input high voltage VINHDual supply only, input coding binary 1, 2, 3 All 2.4 V Digital input low voltage VINLDual supply only, input coding binary 1, 2, 3 All 0.8 V Digital input leakage current IILCDual supply only, input coding binary 1, 2, 3 All 1.0 A Di

31、gital input capacitance CIN Dual supply only, TA= +25C 4 All 8 pF Functional tests See 4.3.1d 7 All Voltage output slew rate 3/ SR Dual and single supply 9, 10, 11 All 2 V/s Voltage output settling time tSLPositive full scale change, dual and single supply, VREF= +10 V 9, 10, 11 All 5.0 s 3/, 6/ Neg

32、ative full scale change, Dual supply 5.0 VREF= +10 V Single supply 7.0 Power supply current IDD1 All 16 mA 2, 3 22 ISSDual supply only 1 -14 2, 3 -20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

33、 DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max

34、Address to WR setup time 3/ t1Dual and single supply, see figure 3 7/ 9, 10, 11 All 0 ns Address to WR hold time 3/ t2Dual and single supply, see figure 3 7/ 9, 10, 11 All 0 ns Data valid to WR setup time 3/ t3Dual and single supply, see figure 3 7/ 9 All 70 ns 10, 11 100 Data valid to WR hold time

35、3/ t4Dual and single supply, see figure 3 7/ 9, 10, 11 All 10 ns Write pulse width 3/ t5Dual and single supply, see figure 3 7/ 9 All 95 ns 10, 11 150 1/ Measurements apply with dual supplies, RL= 2.0 k, and CL= 100 pF, unless otherwise specified. Refer to 1.4 for conditions of dual and single suppl

36、ies. 2/ Includes zero code error, relative accuracy, and full scale error. 3/ If not tested, shall be guaranteed to the limits specified in table I. 4/ Calculated after zero code error has been adjusted out. 5/ Occurs when each DAC is loaded with all logic 1s. 6/ Settling time to 0.5 LSB with VREF=

37、+10 V. 7/ All input rise and fall times measured from 10 percent to 90 percent, tr= tf= 5.0 ns. Timing measurement reference level is VINH+ VINL. 2 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LA

38、ND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device types All Case outlines L 3 Terminal number Terminal symbol 1 VDDNC 2 VOUT8VDD3 VOUT7VOUT84 VOUT6VOUT75 VOUT5VOUT66 VOUT4VOUT57 VOUT3VOUT48 VOUT2NC 9 VOUT1VOUT310 VSSVOUT211 VREFVOUT112 GROUND VSS13 DB7 (

39、MSB) VREF14 DB6 GROUND 15 DB5 NC 16 DB4 DB7 (MSB) 17 DB3 DB6 18 DB2 DB5 19 DB1 DB4 20 DB0 (LSB) DB3 21 WR DB2 22 A2 NC 23 A1 DB1 24 A0 DB0 (LSB) 25 - - - WR 26 - - - A2 27 - - - A1 28 - - - A0 FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted withou

40、t license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Control inputs WR A2 A1 A0 Operation H X X X No operation, device not selected L L L L DAC1 transparent _ L L L DAC1 latched L L L H D

41、AC2 transparent L L H L DAC3 transparent L L H H DAC4 transparent L H L L DAC5 transparent L H L H DAC6 transparent L H H L DAC7 transparent L H H H DAC8 transparent H = High state, L = Low state, X = Dont care, _ = Low to High transition FIGURE 2. Truth table. NOTE: The selected input latch is tran

42、sparent while WR is low, thus invalid data during this time can cause spurious ouputs. FIGURE 3. Write cycle timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88663 DLA LAND AND MARITIME COLUMBU

43、S, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA La

44、nd and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shal

45、l be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and th

46、e acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accorda

47、nce with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test con

48、dition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim elec