DLA SMD-5962-88670 REV E-2010 MICROCIRCUIT MEMORY DIGITAL CMOS ONE-TIME PROGRAMMABLE PROGRAMMABLE ARRAY LOGIC MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add CAGE number 50364 as a supplier for 02 and 03 device types. Add 04 device type. Add CAGE number 1FN41 as a supplier of the K package. Editorial changes throughout entire document. Remove C as a test condition option. 89-08-23 M. A. Frye B Cha

2、nge CIand COvalues in Table I. Incorporate power reset feature. Add 05 device. Add CAGE number 65786 for 04K, 04L and 043 devices. Add footnote 7/ to Table I. Editorial changes throughout entire document. 91-11-06 M. A. Frye C Update drawing to current requirements. Editorial changes throughout. - g

3、ap 01-11-02 Raymond Monnin D Boilerplate update part of 5 year review. ksr 06-08-18 Raymond Monnin E Corrected IILand IIHparameters in Table I. ksr 10-03-29 Charles F. Saffle THE ORIGINAL FRONT PAGE HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6

4、 7 8 9 10 11 PMIC N/A PREPARED BY Jeffery D. Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL

5、, CMOS, ONE-TIME PROGRAMMABLE, PROGRAMMABLE ARRAY LOGIC, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DRAWING APPROVAL DATE 88-07-27 REVISION LEVEL E SIZE A CAGE CODE 67268 5962-88670 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E255-10 Provided by IHSNot for ResaleNo reproducti

6、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88670 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, no

7、n-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88670 01 L X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). Th

8、e device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 C22V10 22-input 10-output 25 ns and-or-logic array 02 C22V10 22-input 10-output 30 ns and-or-logic array 03 C22V10 22-input 10-output 40 ns and-or-logic array 04 C22V10 22-input 10-o

9、utput 20 ns and-or-logic array 05 C22V10 22-input 10-output 15 ns and-or-logic array 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 Flat package L GDIP3-T24 or CDIP

10、4-T24 24 Dual-in-line 3 CQCC1-N28 28 Leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range -2.0 V dc to +7.0 V dc 2/ Output voltage applied range . -0.5 V

11、 dc to +7.0 V dc 2/ Output sink current . 16 mA Thermal resistance, junction-to-case (JC): See MIL-STD-1835 Maximum power dissipation (PD) 3/ . 1.2 W Maximum junction temperature (TJ) . +175C Lead temperature (soldering, 10 seconds maximum) +260C Storage temperature range -65C to +150C Temperature u

12、nder bias . -55C to +125C _ 1/ All voltages referenced to VSS. 2/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 3/ Must withstand the added PDdu

13、e to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88670 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommende

14、d operating conditions. Supply voltage (VCC) 4.5 V dc to 5.5 V dc High level input voltage (VIH) 2.0 V dc minimum Low level input voltage (VIL) . 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The

15、 following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufactu

16、ring, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Micr

17、ocircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this d

18、rawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordan

19、ce with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-3853

20、5 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall

21、 not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The desi

22、gn, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The tru

23、th table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, C, or D (see 4.3), the devices shall be programmed by the manufacturer prio

24、r to test with a minimum of 50 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The truth tables for programmed devices shall be as specified by an attached a

25、ltered item drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88670 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance ch

26、aracteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. Th

27、e electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD P

28、IN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indica

29、tor “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MI

30、L-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate

31、of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent

32、, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing options. Since the device is capable of being programmed by either the manu

33、facturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.10.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and tabl

34、e II. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.10.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item d

35、rawing, shall be satisfied by the manufacturer prior to delivery. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be condu

36、cted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to

37、 the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be

38、 as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88670 DEFENSE S

39、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 7/ VSS= 0 V, -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level

40、output VOHIO= -2.0 mA VIH= 2.0 V 1, 2, 3 All 2.4 V voltage VIL= 0.8 V Low level output VOLIO= 12.0 mA VIH= 2.0 V 1, 2, 3 All 0.5 V voltage VIL= 0.8 V High impedance output IOZVCC= 5.5 V 1, 2, 3 All -40 40 A leakage current 2/ High level input IIHVIH= 5.5 V (excludes I/O pins) 1, 2, 3 All -10 +10 A c

41、urrent Low level input IILVIL= GND (excludes I/O pins) 1, 2, 3 All -10 +10 A current Standby power supply ICCVCC= 5.5 V, VIN= GND 1, 2, 3 01-03 100 mA current 04, 05 120 mA Output short circuit IOSVCC= 5.5 V, VO= 0.5 V 1, 2, 3 All -30 -90 mA current 3/ 4/ Outputs open for unprogrammed device Input c

42、apacitance CIVI= 0 V, VCC= 5.0 V, 4 All pF 4/ 5/ TA= +25C, f = 1 MHz, 10 (see 4.3.1c) Output capacitance COVO= 0 V, VCC= 5.0 V, 4 All pF 4/ 5/ TA= +25C, f = 1 MHz, 10 (see 4.3.1c) Functional test See footnote 4/ of Table IIA 7,8A,8B All Input to output enable tEAVCC= 4.5 V, CL= 5 pF, 9, 10, 11 01 25

43、 ns See figure 3 (circuit A) and 02 30 figure 4 03 40 04 20 05 15 Input to output tER9, 10, 11 01 25 ns disable 02 30 03 40 04 20 05 15 Input or feedback to tPDVCC= 4.5 V, CL= 50 pF, 9, 10, 11 01 25 ns nonregistered output See figure 3 (circuit B) and 02 30 figure 4 03 40 04 20 05 15 Clock to output

44、 tCO9, 10, 11 01, 04 15 ns 02 20 03 25 05 10 See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88670 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET

45、 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 7/ VSS= 0 V, -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Clock period tPVCC= 4.5 V, CL= 50 pF, 9, 10, 11 01 33 ns (tco+ ts) Se

46、e figure 3 (circuit B) and 02 40 figure 4 03 55 04 32 05 22 Clock pulse width tW9, 10, 11 01, 04 15 ns 4/ 6/ 02 20 03 27 05 6 Setup time 4/ 6/ tS9, 10, 11 01 18 ns 02 20 03 30 04 17 05 12 Hold time 4/ 6/ tH9, 10, 11 All 0 ns Maximum clock fMAX9, 10, 11 01 30 MHz frequency 4/ 6/ 02 25 03 18 04 31 05

47、45 Asynchronous reset tAW9, 10, 11 01 25 ns pulse width 02 30 03 40 04 20 05 15 Asynchronous reset tAR9, 10, 11 01 25 ns recovery time 02 30 03 40 04 20 05 15 Asynchronous reset to tAP9, 10, 11 01, 04 25 ns registered output 02 30 reset 03 40 05 20 Power-up reset time 4/ tPRSee figure 5 9, 10, 11 Al

48、l 1 s 1/ All voltages are referenced to ground. 2/ I/O terminal leakage is the worst case of IIXor IOZ. 3/ Only one output shorted at a time. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 5/ All pins not being tested are to be open. 6/ Test applies only to register outputs. 7/ AC testing. Input pu