DLA SMD-5962-88707 REV D-2009 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL PI-BUS TRANSCEIVER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Revised footnote 1 on page 9. Editorial changes throughout. 89-10-05 W. K. Heckman B Made technical changes in table I. Editorial changes throughout. 92-01-27 Monica Poelking C Changes in accordance with NOR 5962-R194-92. 92-04-22 Monica L. Poelk

2、ing D Redrawn with changes. Update drawing to current requirements. Editorial changes throughout. - gap 09-11-04 Charles F. Safflle The original first sheet of this drawing has been replaced. REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 1

3、4 PMIC N/A PREPARED BY Monica L. Poelking DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Ray Monnin APPROVED BY Michael A. Frye MIC

4、ROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, PI-BUS TRANSCEIVER, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-11-14 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-88707 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E315-09 Provided by IHSNot for ResaleNo reproduction or networking permitted

5、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microci

6、rcuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88707 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify t

7、he circuit function as follows: Device type Generic number Circuit function 01 54F776 Octal, bidirectional latched Pi-Bus transceiver 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28

8、 or CDIP2-T28 28 dual-in-line package Y GDFP2-F28 28 flat package 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc to +7.0 V dc VOHoutput level control voltage, A outputs

9、 (VX) . -0.5 V dc to +7.0 V dc Input voltage range: A0- A7, B0- B7. -0.5 V dc to +5.5 V dc All others . -0.5 V dc to +7.0 V dc Input current (IIN) -40 mA to +5.0 mA Voltage applied to output in high state . -0.5 V dc to VCCCurrent applied to output in low state: B0- B7 200 mA A0- A7 40 mA Maximum po

10、wer dissipation (PD) 1/ . 800 mW Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Storage temperature range -65C to +150C Junction temperature (TJ) +175C Lead temperature (soldering, 10 seconds) +300C _ 1/ Must withstand the added PDdue to short-circuit test; e.g., IOS. Provided by IHSNo

11、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) .

12、4.5 V dc to +5.5 V dc Minimum high level input voltage (VIH): B0- B7 1.60 V dc 2/ All others . 2.0 V dc Maximum low level input voltage (VIL): B0- B7. 1.45 V dc 2/ All others . 0.8 V dc Maximum input clamp current (IIK): A0- A7 -40 mA All others . -18 mA Maximum high level output current (IOH): A0-

13、 A7. -3.0 mA Maximum low level output current (IOL): A0- A7. 20 mA B0- B7. 100 mA Minimum setup time, A to LE (ts(H), ts(L) . 5.0 ns Minimum hold time, A to LE (th(H), ts(L) . 0.0 ns Minimum LE pulse width low (tw(L) . 10.0 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and hand

14、books. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits,

15、 Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Sta

16、ndard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text

17、of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 2/ Due to test equipment limitations, actual test conditions are VIH= 1.9 V and V

18、IL= 1.2 V; however, the specified limits are guaranteed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234

19、APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and quali

20、fied manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qualit

21、y Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to ide

22、ntify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal

23、connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and sha

24、ll apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, a

25、ppendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.

26、5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow

27、option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply

28、 shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawi

29、ng. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offsh

30、ore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D

31、 SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max High level output current (B0- B7only) IOHVCC= 5.5 V, VIL= 0.8 V, VIH= 2.0 V, VOH= 2.1 V 1, 2, 3 100 A Power off outpu

32、t current (B0- B7only) IOFFBn= 2.1 V, VCC= 0.0 V, VIL= 0.8 V, VIH= 2.0 V 100 A High level output voltage (A0- A7only) VOHVCC= 4.50 V, VIL= 1.45 V, VIH= 1.60 V 1/ 2/ IOH= -3.0 mA VX= 4.5 V 2.5 4.5 V OH= -0.4 mA VX= 3.13 V 2.5 3.13 IOH= -0.4 mA VX= 3.47 V 2.5 3.47 Low level output voltage A0- A7VOLVCC

33、 4.50 V, VIL= 1.45 V, VIH= 1.60 V 1/ 2/ IOL= 20 mA VX= 4.5 V 0.5 V Low level output voltage B0- B7VCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V IOL= 100 mA 1.15 OL= 4.0 mA 0.40 Input clamp voltage VIKVCC= 4.5 V IIK= -40 mA A0- A7-0.5 V IK= -18 mA All others -1.2 High level input current IIH1VCC= 5.5 V VI= 2.7

34、 V OEA, nOEB and LE 20 A I= 2.1 V B0- B7100 High level input current IIH2VCC= 5.5 V VI= 7.0 V OEA, nOEB and LE 100 A I= 5.5 V A0- A71.0 mA VI= 5.5 V B0- B71.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

35、ROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min M

36、ax Low level input current IILVCC= 5.5 V VI= 0.5 V OEA, nOEB and LE 1, 2, 3 -20 A I= 0.3 V B0- B7-100 Off-state output high current (A0- A7only) IOZHVCC= 5.5 V, VO= 2.7 V 70 A Off-state output low current (A0- A7only) IOZLVCC= 5.5 V, VO= 0.5 V -70 A Short circuit output current (A0- A7only) IOSVCC=

37、5.5 V, OEA = 2.0 V, Bn= 1.6 V, nOEB = 2.7 V 3/ -60 -150 mA High level control current IXVCC= 5.5 V, VX= 5.5 V, A0- A7= LE = OEA = nOEB = 2.7 V, B0- B7= 2.0 V -100 100 mA VCC= 5.5 V, VX= 3.13 and 3.47 V, A0- A7= LE = OEA = nOEB = 2.7 V, B0- B7= 2.0 V -10 10 Supply current (total) ICCH VCC= 5.5 V, VIN

38、 4.5 V 100 mA ICCL VCC= 5.5 V, VIN= 0.5 V 145 CCZ VCC= 5.5 V, VIN= 0.5 V 100 Functional testing See 4.3.1c, VCC= 4.5 V, 5.5 V 7, 8 Propagation delay time, Bnto AntPLH1CL= 50 pF, 4/ RL= 500 , See figures 3 and 4 9 5.5 12.5 ns 10, 11 4.5 13.0 tPHL19 10.5 10, 11 6.0 11.5 Output enable time, OEA to Ant

39、PZH9 8.0 14.5 ns 10, 11 7.0 16.5 tPZL9 8.5 14.5 10, 11 8.5 18.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 RE

40、VISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Output disable time, OEA to AntPHZCL= 50 pF RL= 500 4/ See figures 3 and 4 9 2.0 7.0 ns 10,

41、11 2.0 7.5 tPLZ9 10, 11 2.0 8.0 Propagation delay time, Anto BntPLH2CL= 30 pF 4/ RU= 9.0 See figures 3 and 4 9 2.0 7.5 ns 10, 11 1.5 10.0 tPHL29 3.0 8.0 10, 11 2.5 9.0 Propagation delay time, LE to BntPLH39 3.0 8.5 ns 10, 11 2.0 11.5 tPHL39 3.5 9.0 10, 11 2.5 9.5 Propagation delay time, (enable disa

42、ble time) nOEB to BntPLH49 2.0 7.5 ns 10, 11 1.5 9.5 tPHL49 3.5 10.0 10, 11 3.0 10.5 Transition time, B side tTLH, tTHL9, 10, 11 0.5 5.5 ns 1/ Due to test equipment limitations, actual test conditions are for VIH= 1.9 V and for VIL= 1.2 V; however, the specified test limits and conditions are guaran

43、teed. 2/ VIHand VILare used on B inputs only. All other inputs = 0.8 V or 2.0 V. 3/ Not more than one output should be shorted at a time and the duration of the short circuit condition shall not exceed one second. 4/ For subgroup 9, VCC= 5.0 V and for subgroups 10 and 11, VCC= 4.5 V and 5.5 V. Provi

44、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines X, Y and 3 Terminal number

45、 Terminal symbol 1 VCC2 OEA 3 A04 GND 5 A16 A27 A38 GND 9 A410 A511 GND 12 A613 A714 VX15 0OEB 16 1OEB 17 B718 GND 19 B620 B521 B422 GND 23 B324 B225 GND 26 B127 B028 LE FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

46、STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88707 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Inputs Latch State Outputs Mode AnBn 1/ LE OEA 0OEB 1OEBAnBnH X L L L L H Z H A three-state, data from A to B L X L L L L L Z L A three-state, data

47、from A to B X X H L L L QnZ QnA three-state, latched data to B - - L H L L 2/ 2/ 2/ Feedback: A to B, B to A - H H H L L H 3/ H Off 3/ Preconditioned latch enabling data transfer from B to A - L H H L L H 3/ L Off 3/ Preconditioned latch enabling data transfer from B to A - - H H L L QnQnQnLatch sta

48、te to A and B H X L L H X H Z Off B off and A three-state L X L L H X L Z Off B off and A three-state X X H L H X QnZ Off B off and A three-state - H L H H X H H Off B off, data from B to A - L L H H X L L Off B off, data from B to A - H H H H X QnH Off B off, data from B to A - L H H H X QnL Off B off, data from B to A H X L L X H H Z Off B off and A three-state L X L L X H L Z Off B off and A three-state X X H L X H QnZ Off B off and A three-state - H L H X H H H