1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update, part of 5 year review. ksr 06-08-30 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY
2、 Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 88-
3、09-23 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-88713 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E605-06 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN
4、DARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF
5、-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88713 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: D
6、evice type Generic number 1/ Circuit function tPD01,05,09 C16L8 16-input 8-output AND-OR invert logic array 40,30,20 ns 02,06,10 C16R8 16-input 8-output registered AND-OR logic array 40,30,20 ns 03,07,11 C16R6 16-input 6-output registered AND-OR logic array 40,30,20 ns 04,08,12 C16R4 16-input 4-outp
7、ut registered AND-OR logic array 40,30,20 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20-lead dual-in-line package S GDFP2-F20 or CDFP3-F20 20-lead flat package
8、X CQCC2-N20 20-terminal square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range - -0.5 V dc to +7.0 V dc DC voltage applied to outputs in High Z - -0.5 V dc to +7.0 V dc DC input voltage - -3.0 V
9、dc to +7.0 V dc Output sink current- 24 mA Thermal resistance, junction-to-case (JC):- See MIL-STD-1835 Maximum power dissipation (PD) 1/- 1.0 W Maximum junction temperature (TJ) - +175C Lead temperature (soldering, 10 seconds maximum) +260C Storage temperature range - -65C to +150C Temperature unde
10、r bias range - -55C to +125C 1.4 Recommended operating conditions. Supply voltage (VCC) - 4.5 V dc to 5.5 V dc High-level input voltage (VIH) - 2.0 V dc minimum Low-level input voltage (VIL)- 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C 1/ Must withstand the added PDdue to
11、short circuit test, e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUM
12、ENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFE
13、NSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List
14、 of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA
15、 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.
16、3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified ma
17、nufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Manag
18、ement (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify w
19、hen the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth tab
20、le. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.3), the devices shall be programmed by the manufa
21、cturer prior to test with a minimum of 50 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.2.2 Programmed devices. The truth tables for programmed devices shall be as specified by an
22、 attached altered item drawing. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case op
23、erating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
24、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Group A subgroups Device type Limits Unit Conditions 1/ -55C TC +125C 4.5 V VCC 5.5
25、V unless otherwise specified Min Max Output high voltage VOHVSS= 0 V, IOH= -2.0 mA, 1, 2, 3 All 2.4 V IN= VIH, VILOutput low voltage VOLVCC= 4.5 V, IOL= 12.0 mA, 1, 2, 3 All 0.4 V IN= VIHor VILInput high voltage 2/ VIH1, 2, 3 All 2.0 V Input low voltage 2/ VIL1, 2, 3 All 0.8 V Input leakage current
26、IIXVIN= 5.5 V to GND 1, 2, 3 All -10 10 A Output leakage current IOZVCC= 5.5 V, 1, 2, 3 All -100 100 A OUT= 5.5 V and GND Output short circuit IOSVCC= 5.5 V, 1, 2, 3 All -300 mA current 3/ 4/ VOUT= 0.5 V ICCVCC= 5.5 V, IOUT= 0 mA, 1, 2, 3 All 70 mA Power supply current 5/ IN= GND Input capacitance 4
27、/ CINVIN= 0 V, VCC= 5.0 V 4 All 7 pF TA= +25C, f = 1 MHz Output capacitance 4/ COUT(see 4.3.1c) 4 All 7 pF Input or feedback to tPDVCC= 5.5 V 9, 10, 11 01, 03, 04 40 ns non-registered output See figures 3 and 4 05, 07, 08 30 09, 11, 12 20 Input to output enable tEA9, 10, 11 01, 03, 04 40 ns 05, 07,
28、08 30 09, 11, 12 20 Input to output disable tER9, 10, 11 01, 03, 04 40 ns 4/ 6/ 05, 07, 08 30 09, 11, 12 20 OE to output enable tPZX9, 10, 11 02, 03, 04 25 ns 06, 07, 08 25 10, 11, 12 20 OE to output disable tPXZ9, 10, 11 02, 03, 04 25 ns 4/ 6/ 06, 07, 08 25 10, 11, 12 20 See footnotes at end of tab
29、le. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristic
30、s - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Clock to output 7/ tCOVCC= 5.5 V 9, 10, 11 02, 03, 04 25 ns See figures 3 and 4 06, 07, 08 20 10, 11, 12 15 Input or feedback tSU9, 10, 11 02, 03, 04 35 ns
31、 setup time 7/ 06, 07, 08 25 10, 11, 12 20 Hold time 7/ tH9, 10, 11 02, 03, 04 0 ns 06, 07, 08 0 10, 11, 12 0 Clock period tP9, 10, 11 02, 03, 04 60 ns 4/ 7/ 06, 07, 08 45 10, 11, 12 35 Clock width 4/ 7/ tW9, 10, 11 02, 03, 04 25 ns 06, 07, 08 20 10, 11, 12 12 Maximum frequency fMAX9, 10, 11 02, 03,
32、 04 16.5 MHz 4/ 7/ 06, 07, 08 22 10, 11, 12 28.5 1/ AC test are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load on figure 3, configuration A. 2/ These are absolute values with respect to device ground a
33、nd all overshoots due to system or tester noise are included. 3/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed one second. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore sh
34、all be guaranteed to the limits specified in table I. 5/ To calculate ICCat any given operating frequency, use 70 mA + ICC(AC), where ICC(AC) = (0.6 mA/MHz) x (operating frequency in MHz). 6/ Transition is measured at steady state high level -500 mV or steady state low level +500 mV on the output fr
35、om the 1.5 V level on the input and the output load on figure 3, configuration B. 7/ Test applies only to registered outputs. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMB
36、US COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the
37、 entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The comp
38、liance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of
39、 supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A
40、 certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC
41、, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing options. Since the device is capable of being programmed by ei
42、ther the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing. 3.10.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2
43、.2.1 and table II. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.10.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the a
44、ltered item drawing, shall be satisfied by the manufacturer prior to delivery. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and s
45、hall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be
46、 made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters sha
47、ll be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FO
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