DLA SMD-5962-88759 REV B-2009 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS QUAD D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 01-12-11 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 09-04-23 Thomas M. Hess REV SHET REV SHET REV STATUS REV B B B B B B B B B B B OF SHE

2、ETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Monica L. Poelking CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES

3、OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-07-31 MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, QUAD D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-88759 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E276-09 P

4、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device r

5、equirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88759 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead

6、finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HCT173 Quad D-type flip-flop with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-18

7、35 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC inp

8、ut voltage range (VIN) . -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) . 35 mA DC VCCor GND current. 70 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 4/ Lead tempera

9、ture (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Input voltage range (VIN) . 0.0 V to VCCOutput voltage range (VOUT) 0.0 V to

10、 VCCCase operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf): VCC= 4.5 V 0 to 500 ns _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unles

11、s otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to + 125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproducti

12、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Maximum clock frequency (fMAX): TC= +25C VCC

13、= 4.5 V dc 20 MHz TC= -55C, +125C VCC= 4.5 V dc 13 MHz Minimum removal time, MR to CP (tREM): TC= +25C VCC= 4.5 V dc 12 ns TC= -55C, +125C VCC= 4.5 V dc 18 ns Minimum setup time, Dn to CP (ts): TC= +25C VCC= 4.5 V dc 12 ns TC= -55C, +125C VCC= 4.5 V dc 18 ns Minimum setup time, En to CP (ts): TC= +2

14、5C VCC= 4.5 V dc 18 ns TC= -55C, +125C VCC= 4.5 V dc 27 ns Minimum hold time, Dn to CP (th): TC= +25C VCC= 4.5 V dc 0 ns TC= -55C, +125C VCC= 4.5 V dc 0 ns Minimum hold time, En to CP (th): TC= +25C VCC= 4.5 V dc 0 ns TC= -55C, +125C VCC= 4.5 V dc 0 ns Minimum pulse width, MR (tw): TC= +25C VCC= 4.5

15、 V dc 15 ns TC= -55C, +125C VCC= 4.5 V dc 22 ns Minimum pulse width, CP (tw): TC= +25C VCC= 4.5 V dc 25 ns TC= -55C, +125C VCC= 4.5 V dc 38 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUP

16、PLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherw

17、ise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1

18、835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Sta

19、ndardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, superse

20、des applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing th

21、at is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval

22、 in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or

23、“QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s

24、). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2

25、.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full cas

26、e operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test

27、 requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In ad

28、dition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marke

29、d on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance s

30、hall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-P

31、RF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be r

32、equired for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the revie

33、wer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristi

34、cs. Test Symbol Test conditions -55C TC+125C unless otherwise specified 1/ Group A subgroups Limits Unit Min Max VIN= 2.0 V or 0.8 V IO= 20 A VCC= 4.5 V 1, 2, 3 4.4 High level output voltage VOHVIN= 2.0 V or 0.8 V IO= 6.0 mA VCC= 4.5 V 1, 2, 3 3.7 V VCC= 4.5 V 1, 2, 3 0.1 Low level output voltage VO

35、LVIN= 2.0 V or 0.8 V, IO= 20 A VIN= 2.0 V or 0.8 V, IO= 6.0 mA VCC= 4.5 V 1, 2, 3 0.4 V High level input voltage VIH2/ VCC= 4.5 V 1, 2, 3 2.0 V Low level input voltage VIL2/ VCC= 4.5 V 1, 2, 3 0.8 V Input capacitance CINVIN= 0.0 V, TC= +25C See 4.3.1c 4 10 pF Three-state output capacitance COUTVIN=

36、0.0 V, TC= +25C See 4.3.1c 4 20 pF Quiescent current ICCVCC= 5.5 V VIN= VCCor GND 1, 2, 3 160 A Input leakage current IINVCC= 5.5 V VIN= VCCor GND 1, 2, 3 1.0 A Three-state output off-state leakage current IOZVCC= 5.5 V, VIN= 2.0 V or 0.8 V VOUT= VCCor GND 1, 2, 3 10.0 A Additional quiescent current

37、 ICCAny one input VIN= 2.4 V Other inputs VIN= VCCor GND VCC= 5.5 V IOUT= 0.0 A 1, 2, 3 3.0 mA Functional tests See 4.3.1d 7, 8 9 43 Propagation delay time, CP to Qn tPHL1, tPLH1VCC= 4.5 V CL= 50 pF See figure 4 10, 11 65 ns 9 37 Propagation delay time, MR to Qn tPHL2VCC= 4.5 V CL= 50 pF See figure

38、4 10, 11 56 ns 9 30 tPLZ, tPHZ10, 11 45 ns 9 35 Propagation delay time, OEn to Qn tPZL, tPZHVCC= 4.5 V CL= 50 pF See figure 4 10, 11 53 ns 9 12 Transition time high-to-low, low-to-high tTHL, tTLH3/ TC= +25C CL= 50 pF See figure 4 10, 11 18 ns See footnotes on next sheet. Provided by IHSNot for Resal

39、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ For a power supp

40、ly of 5 V 10% the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V respectively. 2/ VIHand VILtests are not required if applied as a forcing function for VOHand VO

41、L. 3/ Transition time (tTHL, tTLH), if not tested, shall be guaranteed to the specified limits in table I. Device type 01 Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE1 OE2 Q0 Q1 Q2 Q3 CP GND E1 E2 D3 D2 D1 D0 MR VCCPin description Terminal symbol Descripti

42、on Dn (n = 0 to 3) Data inputs Qn (n = 0 to 3) Data outputs CP Clock pulse input MR Master reset input OEn (n = 1 to 2) Output enable inputs (active low) En (n = 1 to 2) Enable inputs (active low) FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

43、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Inputs Outputs Data enable Data MR CP E1 E2 Dn Qn H L L L L L X L X X H X L L X X X H L L X X X X L H L Q0Q0Q0L H Note: W

44、hen either OE1 or OE2 (or both) is (are) high, the output is disabled to the high-impedance state, however, sequential operation of the flip-flops is not affected. H = High voltage level L = Low voltage level X = Irrelevant = Low to high level transition Q0= The level of Q before the indicated stead

45、y-state input conditions were established. FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI

46、ON LEVEL B SHEET 9 DSCC FORM 2234 APR 97 PARAMETER RLCLS1 S2 tPHZ, tPZH1 k 50 pF Open Closed tPLZ, tPZL1 k 50 pF Closed Open tPLH, tPHL50 pF Open Open tTLH, tTHL50 pF Open Open NOTES: 1. CL= 50 pF minimum or equivalent (includes probe and test fixture capacitance). 2. RL= 1 k or equivalent. 3. Input

47、 signal from pulse generator: VIN= 0.0 V to VCC; PRR 1 MHz; ZO= 50; tr= 6.0 ns; tf= 6.0 ns; tr and it shall be measured from 0.1 VCCto 0.9 VCCand from 0.9 VCCto 0.1 VCC, respectively; duty cycle = 50 percent. 4. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 5. The outputs

48、are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88759 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance